
Mandish K. Randhawa
Examiner (ID: 12075, Phone: (571)270-5650 , Office: P/2475 )
| Most Active Art Unit | 2477 |
| Art Unit(s) | 2419, 2415, 2475, 2477 |
| Total Applications | 630 |
| Issued Applications | 361 |
| Pending Applications | 97 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12054281
[patent_doc_number] => 20170330624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'MEMORY DEVICE HAVING VERTICAL STRUCTURE AND MEMORY SYSTEM INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/433310
[patent_app_country] => US
[patent_app_date] => 2017-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 13988
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433310
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/433310 | Memory device having vertical structure and memory system including the same | Feb 14, 2017 | Issued |
Array
(
[id] => 11897950
[patent_doc_number] => 09767889
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-09-19
[patent_title] => 'Programmable pad capacitance for supporting bidirectional signaling from unterminated endpoints'
[patent_app_type] => utility
[patent_app_number] => 15/433814
[patent_app_country] => US
[patent_app_date] => 2017-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3013
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433814
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/433814 | Programmable pad capacitance for supporting bidirectional signaling from unterminated endpoints | Feb 14, 2017 | Issued |
Array
(
[id] => 11665939
[patent_doc_number] => 20170154658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-01
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/432287
[patent_app_country] => US
[patent_app_date] => 2017-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7032
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432287
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/432287 | Semiconductor memory device | Feb 13, 2017 | Issued |
Array
(
[id] => 12019478
[patent_doc_number] => 09812187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Termination topology of memory system and associated memory module and control method'
[patent_app_type] => utility
[patent_app_number] => 15/424882
[patent_app_country] => US
[patent_app_date] => 2017-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3154
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424882
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/424882 | Termination topology of memory system and associated memory module and control method | Feb 4, 2017 | Issued |
Array
(
[id] => 11974424
[patent_doc_number] => 20170278578
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-28
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/424810
[patent_app_country] => US
[patent_app_date] => 2017-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 23094
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424810
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/424810 | Semiconductor memory device | Feb 3, 2017 | Issued |
Array
(
[id] => 11847346
[patent_doc_number] => 09734904
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-15
[patent_title] => 'Digital low drop-out regulator and resistive memory device using the same'
[patent_app_type] => utility
[patent_app_number] => 15/423456
[patent_app_country] => US
[patent_app_date] => 2017-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 3446
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423456
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/423456 | Digital low drop-out regulator and resistive memory device using the same | Feb 1, 2017 | Issued |
Array
(
[id] => 16563767
[patent_doc_number] => 10889122
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-12
[patent_title] => Accessing memory units in a memory bank
[patent_app_type] => utility
[patent_app_number] => 16/480178
[patent_app_country] => US
[patent_app_date] => 2017-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9134
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16480178
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/480178 | Accessing memory units in a memory bank | Jan 30, 2017 | Issued |
Array
(
[id] => 11622874
[patent_doc_number] => 20170133061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'REGISTER FILES INCLUDING DISTRIBUTED CAPACITOR CIRCUIT BLOCKS'
[patent_app_type] => utility
[patent_app_number] => 15/413171
[patent_app_country] => US
[patent_app_date] => 2017-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8263
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413171
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/413171 | Register files including distributed capacitor circuit blocks | Jan 22, 2017 | Issued |
Array
(
[id] => 11622874
[patent_doc_number] => 20170133061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'REGISTER FILES INCLUDING DISTRIBUTED CAPACITOR CIRCUIT BLOCKS'
[patent_app_type] => utility
[patent_app_number] => 15/413171
[patent_app_country] => US
[patent_app_date] => 2017-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8263
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413171
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/413171 | Register files including distributed capacitor circuit blocks | Jan 22, 2017 | Issued |
Array
(
[id] => 11607810
[patent_doc_number] => 20170125113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/405285
[patent_app_country] => US
[patent_app_date] => 2017-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 21125
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405285
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/405285 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY | Jan 11, 2017 | Abandoned |
Array
(
[id] => 11592640
[patent_doc_number] => 20170117052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES'
[patent_app_type] => utility
[patent_app_number] => 15/401858
[patent_app_country] => US
[patent_app_date] => 2017-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9701
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401858
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/401858 | Non-volatile semiconductor memory having multiple external power supplies | Jan 8, 2017 | Issued |
Array
(
[id] => 12293475
[patent_doc_number] => 09934844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-03
[patent_title] => SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
[patent_app_type] => utility
[patent_app_number] => 15/396341
[patent_app_country] => US
[patent_app_date] => 2016-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 12023
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396341
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/396341 | SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter | Dec 29, 2016 | Issued |
Array
(
[id] => 13018785
[patent_doc_number] => 10032507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
[patent_app_type] => utility
[patent_app_number] => 15/396339
[patent_app_country] => US
[patent_app_date] => 2016-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 12017
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396339
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/396339 | SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter | Dec 29, 2016 | Issued |
Array
(
[id] => 12040246
[patent_doc_number] => 09818480
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-14
[patent_title] => 'Resistance change memory cell circuits and methods'
[patent_app_type] => utility
[patent_app_number] => 15/390645
[patent_app_country] => US
[patent_app_date] => 2016-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8407
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390645
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/390645 | Resistance change memory cell circuits and methods | Dec 25, 2016 | Issued |
Array
(
[id] => 11495196
[patent_doc_number] => 20170069381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 15/354822
[patent_app_country] => US
[patent_app_date] => 2016-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5947
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354822
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/354822 | Systems, methods and devices for programming a multilevel resistive memory cell | Nov 16, 2016 | Issued |
Array
(
[id] => 13111505
[patent_doc_number] => 10074410
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-11
[patent_title] => Integrated circuit using shaping and timing circuitries
[patent_app_type] => utility
[patent_app_number] => 15/282532
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 8605
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282532
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282532 | Integrated circuit using shaping and timing circuitries | Sep 29, 2016 | Issued |
Array
(
[id] => 11397768
[patent_doc_number] => 20170018304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-19
[patent_title] => 'APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 15/282484
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7041
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282484
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282484 | Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors | Sep 29, 2016 | Issued |
Array
(
[id] => 12950305
[patent_doc_number] => 09836227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-05
[patent_title] => Method and system for accessing a flash memory device
[patent_app_type] => utility
[patent_app_number] => 15/273122
[patent_app_country] => US
[patent_app_date] => 2016-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 13597
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273122
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/273122 | Method and system for accessing a flash memory device | Sep 21, 2016 | Issued |
Array
(
[id] => 11974701
[patent_doc_number] => 20170278855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-28
[patent_title] => 'ONE-TIME PROGRAMMING CELL'
[patent_app_type] => utility
[patent_app_number] => 15/261252
[patent_app_country] => US
[patent_app_date] => 2016-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5551
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261252
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/261252 | One-time programming cell | Sep 8, 2016 | Issued |
Array
(
[id] => 11847326
[patent_doc_number] => 09734883
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-15
[patent_title] => 'Reference circuit and MRAM'
[patent_app_type] => utility
[patent_app_number] => 15/261242
[patent_app_country] => US
[patent_app_date] => 2016-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261242
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/261242 | Reference circuit and MRAM | Sep 8, 2016 | Issued |