Mandish K. Randhawa

Array ( [id] => 11578433 [patent_doc_number] => 09633701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Resistor switching circuit, storage circuit, and consumable chip' [patent_app_type] => utility [patent_app_number] => 15/122722 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15122722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11214531 [patent_doc_number] => 09443570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Memory apparatus with training function and memory system using the same' [patent_app_type] => utility [patent_app_number] => 14/950372 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11014059 [patent_doc_number] => 20160211013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'BIT LINE PRECHARGING CIRCUIT, STATIC RAM, ELECTRONIC DEVICE, AND STATIC RAM BIT LINE PRECHARGING METHOD' [patent_app_type] => utility [patent_app_number] => 14/951042 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14951042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10990925 [patent_doc_number] => 20160187870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'AUTOMATED MANUFACTURING SYSTEM WITH JOB PACKAGING MECHANISM AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/945399 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11265690 [patent_doc_number] => 09489990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'Adaptive non-volatile memory programming' [patent_app_type] => utility [patent_app_number] => 14/943566 [patent_app_country] => US [patent_app_date] => 2015-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1860 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14943566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11252779 [patent_doc_number] => 09478290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Memory device and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/938394 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15948 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802507 [patent_doc_number] => 20160148664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'TAMPER-RESISTANT NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/938022 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 32900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11391605 [patent_doc_number] => 09552854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-24 [patent_title] => 'Register files including distributed capacitor circuit blocks' [patent_app_type] => utility [patent_app_number] => 14/937010 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8233 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11495208 [patent_doc_number] => 20170069393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/937070 [patent_app_country] => US [patent_app_date] => 2015-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11214538 [patent_doc_number] => 09443576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Josephson magnetic random access memory with an inductive-shunt' [patent_app_type] => utility [patent_app_number] => 14/935862 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 7 [patent_no_of_words] => 9957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10787178 [patent_doc_number] => 20160133334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'READ-THRESHOLD CALIBRATION IN A SOLID STATE STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/936340 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10717931 [patent_doc_number] => 20160064078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 14/936186 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5901 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14936186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11187323 [patent_doc_number] => 09418731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Memory management method, memory storage device and memory control circuit unit' [patent_app_type] => utility [patent_app_number] => 14/934154 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 8576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10717937 [patent_doc_number] => 20160064084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'Programming Memory With Reduced Short-Term Charge Loss' [patent_app_type] => utility [patent_app_number] => 14/925473 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11770161 [patent_doc_number] => 09378849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Controller to detect malfunctioning address of memory device' [patent_app_type] => utility [patent_app_number] => 14/918148 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11725026 [patent_doc_number] => 09697887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter' [patent_app_type] => utility [patent_app_number] => 14/884451 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 12840 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14884451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11259174 [patent_doc_number] => 09484076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features' [patent_app_type] => utility [patent_app_number] => 14/881098 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8255 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11802107 [patent_doc_number] => 09542997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Memory architecture with local and global control circuitry' [patent_app_type] => utility [patent_app_number] => 14/877278 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 39 [patent_no_of_words] => 16104 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14613501 [patent_doc_number] => 10359445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Method and apparatus for measuring the speed of an electronic device [patent_app_type] => utility [patent_app_number] => 14/875920 [patent_app_country] => US [patent_app_date] => 2015-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11233536 [patent_doc_number] => 09460767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/871063 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871063 [rel_patent_id] =>[rel_patent_doc_number] =>)