Search

Mandy C. Louie

Examiner (ID: 14176, Phone: (571)270-5353 , Office: P/1715 )

Most Active Art Unit
1715
Art Unit(s)
1715, 1718, 1792
Total Applications
611
Issued Applications
264
Pending Applications
57
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15920109 [patent_doc_number] => 10657297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Part number consolidation in printed circuit board assembly design [patent_app_type] => utility [patent_app_number] => 15/996083 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/996083
Part number consolidation in printed circuit board assembly design May 31, 2018 Issued
Array ( [id] => 15639261 [patent_doc_number] => 10592624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Efficient mechanism of fault qualification using formal verification [patent_app_type] => utility [patent_app_number] => 15/996307 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/996307
Efficient mechanism of fault qualification using formal verification May 31, 2018 Issued
Array ( [id] => 15387395 [patent_doc_number] => 10534887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-14 [patent_title] => Power domain placement of circuit components in advance node custom design [patent_app_type] => utility [patent_app_number] => 15/994255 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994255
Power domain placement of circuit components in advance node custom design May 30, 2018 Issued
Array ( [id] => 14556235 [patent_doc_number] => 10346579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Interactive routing of connections in circuit using auto welding and auto cloning [patent_app_type] => utility [patent_app_number] => 15/982995 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 10376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982995
Interactive routing of connections in circuit using auto welding and auto cloning May 16, 2018 Issued
Array ( [id] => 15701585 [patent_doc_number] => 10606972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Method, design program, and design apparatus of a high level synthesis process of a circuit [patent_app_type] => utility [patent_app_number] => 15/968327 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 10978 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968327
Method, design program, and design apparatus of a high level synthesis process of a circuit Apr 30, 2018 Issued
Array ( [id] => 13556975 [patent_doc_number] => 20180330035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => COMPONENT RETRIEVE DEVICE AND COMPONENT RETRIEVE METHOD [patent_app_type] => utility [patent_app_number] => 15/967620 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967620
Component retrieve device and component retrieve method Apr 30, 2018 Issued
Array ( [id] => 13406213 [patent_doc_number] => 20180254649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => BATTERY CHARGER OPERATING METHOD AND METHOD USABLE WITH PLURAL DIFFERENT POWER SUPPLIES [patent_app_type] => utility [patent_app_number] => 15/963768 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963768
Battery charger operating method and method usable with plural different power supplies Apr 25, 2018 Issued
Array ( [id] => 15533315 [patent_doc_number] => 20200058963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => INTRINSICALLY SAFE BATTERY [patent_app_type] => utility [patent_app_number] => 16/487061 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487061
Intrinsically safe battery Apr 10, 2018 Issued
Array ( [id] => 14935777 [patent_doc_number] => 20190303526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => GLOBAL ROUTING OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/940485 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940485
Global routing optimization Mar 28, 2018 Issued
Array ( [id] => 14935763 [patent_doc_number] => 20190303519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => METHOD AND SYSTEM FOR IMPLEMENTATION OF USER LOGIC IN A FIELD PROGRAMMABLE GATE ARRAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/940574 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940574 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940574
Method and system for implementation of user logic in a field programmable gate array device Mar 28, 2018 Issued
Array ( [id] => 14935771 [patent_doc_number] => 20190303523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Multi-Tier Co-Placement for Integrated Circuitry [patent_app_type] => utility [patent_app_number] => 15/939047 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939047
Multi-tier co-placement for integrated circuitry Mar 27, 2018 Issued
Array ( [id] => 15313671 [patent_doc_number] => 10521542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Computer-readable recording medium storing electrical design support program, electrical design support method, and information processing apparatus [patent_app_type] => utility [patent_app_number] => 15/936956 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8297 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/936956
Computer-readable recording medium storing electrical design support program, electrical design support method, and information processing apparatus Mar 26, 2018 Issued
Array ( [id] => 15953311 [patent_doc_number] => 10664565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Method and system of expanding set of standard cells which comprise a library [patent_app_type] => utility [patent_app_number] => 15/936712 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 18459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/936712
Method and system of expanding set of standard cells which comprise a library Mar 26, 2018 Issued
Array ( [id] => 13320663 [patent_doc_number] => 20180211869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => DESIGN-AWARE PATTERN DENSITY CONTROL IN DIRECTED SELF-ASSEMBLY GRAPHOEPITAXY PROCESS [patent_app_type] => utility [patent_app_number] => 15/926274 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926274
Design-aware pattern density control in directed self-assembly graphoepitaxy process Mar 19, 2018 Issued
Array ( [id] => 14484085 [patent_doc_number] => 10328806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Automobile charger [patent_app_type] => utility [patent_app_number] => 15/923219 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923219
Automobile charger Mar 15, 2018 Issued
Array ( [id] => 14873081 [patent_doc_number] => 20190286782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SCALABLE CONNECTIVITY VERIFICATION USING CONDITIONAL CUT-POINTS [patent_app_type] => utility [patent_app_number] => 15/922272 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922272
Scalable connectivity verification using conditional cut-points Mar 14, 2018 Issued
Array ( [id] => 14473425 [patent_doc_number] => 20190188357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => CHIP TEMPERATURE COMPUTATION METHOD AND CHIP TEMPERATURE COMPUTATION DEVICE [patent_app_type] => utility [patent_app_number] => 15/922910 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922910
Chip temperature computation method and chip temperature computation device Mar 14, 2018 Issued
Array ( [id] => 15940505 [patent_doc_number] => 20200161886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => POWER FEED UNIT AND POWER FEEDING METHOD [patent_app_type] => utility [patent_app_number] => 16/604676 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16604676 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/604676
Power feed unit and power feeding method Mar 4, 2018 Issued
Array ( [id] => 15358633 [patent_doc_number] => 10527929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Methods of improving optical proximity correction models and methods of fabricating semiconductor devices using the same [patent_app_type] => utility [patent_app_number] => 15/885134 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 10333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885134
Methods of improving optical proximity correction models and methods of fabricating semiconductor devices using the same Jan 30, 2018 Issued
Array ( [id] => 14657169 [patent_doc_number] => 20190235713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SYSTEMS AND METHODS FOR TRACKING PROGRESS OF DESIGN OF A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/885730 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885730 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885730
Systems and methods for tracking progress of design of a semiconductor device Jan 30, 2018 Issued
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