Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10575900
[patent_doc_number] => 09298543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Electrically erasable programmable memory device that generates error-detection information'
[patent_app_type] => utility
[patent_app_number] => 14/806011
[patent_app_country] => US
[patent_app_date] => 2015-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11932
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14806011
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/806011 | Electrically erasable programmable memory device that generates error-detection information | Jul 21, 2015 | Issued |
Array
(
[id] => 11614458
[patent_doc_number] => 09652315
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-05-16
[patent_title] => 'Multi-core RAM error detection and correction (EDAC) test'
[patent_app_type] => utility
[patent_app_number] => 14/805229
[patent_app_country] => US
[patent_app_date] => 2015-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3018
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14805229
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/805229 | Multi-core RAM error detection and correction (EDAC) test | Jul 20, 2015 | Issued |
Array
(
[id] => 14012963
[patent_doc_number] => 10224965
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => Apparatus for transmitting data in interleave division multiple access (IDMA) system
[patent_app_type] => utility
[patent_app_number] => 15/519862
[patent_app_country] => US
[patent_app_date] => 2015-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 30
[patent_no_of_words] => 26925
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15519862
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/519862 | Apparatus for transmitting data in interleave division multiple access (IDMA) system | Jul 20, 2015 | Issued |
Array
(
[id] => 11891691
[patent_doc_number] => 09762265
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-12
[patent_title] => 'Methods and systems for enhanced detection of electronic tracking messages'
[patent_app_type] => utility
[patent_app_number] => 14/802373
[patent_app_country] => US
[patent_app_date] => 2015-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8734
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802373
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/802373 | Methods and systems for enhanced detection of electronic tracking messages | Jul 16, 2015 | Issued |
Array
(
[id] => 12019515
[patent_doc_number] => 09812224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Data storage system, data storage device and RAID controller'
[patent_app_type] => utility
[patent_app_number] => 14/800614
[patent_app_country] => US
[patent_app_date] => 2015-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9609
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800614
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/800614 | Data storage system, data storage device and RAID controller | Jul 14, 2015 | Issued |
Array
(
[id] => 11565513
[patent_doc_number] => 09628114
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Length-compatible extended polar codes'
[patent_app_type] => utility
[patent_app_number] => 14/794059
[patent_app_country] => US
[patent_app_date] => 2015-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4600
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794059
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/794059 | Length-compatible extended polar codes | Jul 7, 2015 | Issued |
Array
(
[id] => 13186595
[patent_doc_number] => 10108819
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-10-23
[patent_title] => Cross-datacenter extension of grid encoded data storage systems
[patent_app_type] => utility
[patent_app_number] => 14/789789
[patent_app_country] => US
[patent_app_date] => 2015-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 38395
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 305
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789789
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/789789 | Cross-datacenter extension of grid encoded data storage systems | Jun 30, 2015 | Issued |
Array
(
[id] => 11811335
[patent_doc_number] => 09715908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-25
[patent_title] => 'Controller for a solid-state drive, and related solid-state drive'
[patent_app_type] => utility
[patent_app_number] => 14/789518
[patent_app_country] => US
[patent_app_date] => 2015-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 11012
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789518
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/789518 | Controller for a solid-state drive, and related solid-state drive | Jun 30, 2015 | Issued |
Array
(
[id] => 11883497
[patent_doc_number] => 09754677
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-05
[patent_title] => 'Semiconductor memory device, memory system including the same, and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/789608
[patent_app_country] => US
[patent_app_date] => 2015-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5176
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789608
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/789608 | Semiconductor memory device, memory system including the same, and operating method thereof | Jun 30, 2015 | Issued |
Array
(
[id] => 11818665
[patent_doc_number] => 09722635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Controller for a solid-state drive, and related solid-state'
[patent_app_type] => utility
[patent_app_number] => 14/789522
[patent_app_country] => US
[patent_app_date] => 2015-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 12805
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789522
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/789522 | Controller for a solid-state drive, and related solid-state | Jun 30, 2015 | Issued |
Array
(
[id] => 11366050
[patent_doc_number] => 20170004031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'VARIABLE CODE RATE SOLID-STATE DRIVE'
[patent_app_type] => utility
[patent_app_number] => 14/789017
[patent_app_country] => US
[patent_app_date] => 2015-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5415
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789017
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/789017 | Variable code rate solid-state drive | Jun 30, 2015 | Issued |
Array
(
[id] => 11801392
[patent_doc_number] => 09542269
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-01-10
[patent_title] => 'Controller controlling semiconductor memory device and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/754014
[patent_app_country] => US
[patent_app_date] => 2015-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 17
[patent_no_of_words] => 10334
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754014
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/754014 | Controller controlling semiconductor memory device and operating method thereof | Jun 28, 2015 | Issued |
Array
(
[id] => 10496187
[patent_doc_number] => 20150381209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'Code Block Segmentation and Configuration for Concatenated Turbo and RS Coding'
[patent_app_type] => utility
[patent_app_number] => 14/749030
[patent_app_country] => US
[patent_app_date] => 2015-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14749030
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/749030 | Code block segmentation and configuration for concatenated turbo and RS coding | Jun 23, 2015 | Issued |
Array
(
[id] => 14037759
[patent_doc_number] => 10230646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-12
[patent_title] => Method and apparatus for transmitting and receiving packets in broadcast and communication system
[patent_app_type] => utility
[patent_app_number] => 15/320546
[patent_app_country] => US
[patent_app_date] => 2015-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 5713
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15320546
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/320546 | Method and apparatus for transmitting and receiving packets in broadcast and communication system | Jun 21, 2015 | Issued |
Array
(
[id] => 11049714
[patent_doc_number] => 20160246673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-25
[patent_title] => 'CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/743914
[patent_app_country] => US
[patent_app_date] => 2015-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 17549
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743914
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/743914 | Controller, semiconductor memory system and operating method thereof | Jun 17, 2015 | Issued |
Array
(
[id] => 11898964
[patent_doc_number] => 09768911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'System and method for designing constellations and use thereof'
[patent_app_type] => utility
[patent_app_number] => 14/737336
[patent_app_country] => US
[patent_app_date] => 2015-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 5469
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737336
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/737336 | System and method for designing constellations and use thereof | Jun 10, 2015 | Issued |
Array
(
[id] => 11280608
[patent_doc_number] => 09497097
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-15
[patent_title] => 'Inserting sequence numbers into data blocks merged from data streams'
[patent_app_type] => utility
[patent_app_number] => 14/734632
[patent_app_country] => US
[patent_app_date] => 2015-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1543
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734632
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/734632 | Inserting sequence numbers into data blocks merged from data streams | Jun 8, 2015 | Issued |
Array
(
[id] => 10708909
[patent_doc_number] => 20160055056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION'
[patent_app_type] => utility
[patent_app_number] => 14/729656
[patent_app_country] => US
[patent_app_date] => 2015-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 13450
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729656
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/729656 | Memory device having error notification function | Jun 2, 2015 | Issued |
Array
(
[id] => 10376604
[patent_doc_number] => 20150261611
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY'
[patent_app_type] => utility
[patent_app_number] => 14/728588
[patent_app_country] => US
[patent_app_date] => 2015-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1079
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728588
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/728588 | Forward error correction with configurable latency | Jun 1, 2015 | Issued |
Array
(
[id] => 10376603
[patent_doc_number] => 20150261610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'SELF-DESCRIBING DATA BLOCKS OF A MINIMUM ATOMIC WRITE SIZE FOR A DATA STORE'
[patent_app_type] => utility
[patent_app_number] => 14/727644
[patent_app_country] => US
[patent_app_date] => 2015-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 16175
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727644
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/727644 | Self-describing data blocks of a minimum atomic write size for a data store | May 31, 2015 | Issued |