Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5325706 [patent_doc_number] => 20090063696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'SYSTEM AND METHODS FOR HIGH RATE HARDWARE-ACCELERATED NETWORK PROTOCOL PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/140101 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 26419 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20090063696.pdf [firstpage_image] =>[orig_patent_app_number] => 12140101 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/140101
System and methods for high rate hardware-accelerated network protocol processing Jun 15, 2008 Issued
Array ( [id] => 8235582 [patent_doc_number] => 08201041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Transmission control methods and devices for communication systems' [patent_app_type] => utility [patent_app_number] => 12/137792 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 16572 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201041.pdf [firstpage_image] =>[orig_patent_app_number] => 12137792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137792
Transmission control methods and devices for communication systems Jun 11, 2008 Issued
Array ( [id] => 5344407 [patent_doc_number] => 20090183057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'OFFLOADING iSCSI WITHOUT TOE' [patent_app_type] => utility [patent_app_number] => 12/137919 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10353 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20090183057.pdf [firstpage_image] =>[orig_patent_app_number] => 12137919 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137919
Upper layer protocol (ULP) offloading for internet small computer system interface (ISCSI) without TCP offload engine (TOE) Jun 11, 2008 Issued
Array ( [id] => 5375961 [patent_doc_number] => 20090313522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'METHOD AND APPARATUS FOR LOW LATENCY TURBO CODE ENCODING' [patent_app_type] => utility [patent_app_number] => 12/136930 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10773 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313522.pdf [firstpage_image] =>[orig_patent_app_number] => 12136930 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136930
Method and apparatus for low latency turbo code encoding Jun 10, 2008 Issued
Array ( [id] => 4761293 [patent_doc_number] => 20080313519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Method and Apparatus for Improving Hybrid Automatic Repeat Request Operation in a Wireless Communications System' [patent_app_type] => utility [patent_app_number] => 12/136066 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4181 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313519.pdf [firstpage_image] =>[orig_patent_app_number] => 12136066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136066
Method and apparatus for improving hybrid automatic repeat request operation in a wireless communications system Jun 9, 2008 Issued
Array ( [id] => 5369998 [patent_doc_number] => 20090307557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Packet Re-transmission Controller for Block Acknowledgement in a Communications System' [patent_app_type] => utility [patent_app_number] => 12/134213 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2773 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307557.pdf [firstpage_image] =>[orig_patent_app_number] => 12134213 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134213
Packet Re-transmission controller for block acknowledgement in a communications system Jun 5, 2008 Issued
Array ( [id] => 8389097 [patent_doc_number] => 08266508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Computational efficient convolutional coding with rate matching' [patent_app_type] => utility [patent_app_number] => 12/133498 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3519 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12133498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133498
Computational efficient convolutional coding with rate matching Jun 4, 2008 Issued
Array ( [id] => 4889093 [patent_doc_number] => 20080263425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Turbo LDPC Decoding' [patent_app_type] => utility [patent_app_number] => 12/131928 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11636 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263425.pdf [firstpage_image] =>[orig_patent_app_number] => 12131928 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131928
Turbo LDPC decoding Jun 2, 2008 Issued
Array ( [id] => 5305818 [patent_doc_number] => 20090300470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'MEMORY ARCHITECTURE FOR HIGH THROUGHPUT RS DECODING FOR MEDIAFLO RECEIVERS' [patent_app_type] => utility [patent_app_number] => 12/131400 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300470.pdf [firstpage_image] =>[orig_patent_app_number] => 12131400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131400
Memory architecture for high throughput RS decoding for MediaFLO receivers Jun 1, 2008 Issued
Array ( [id] => 4712999 [patent_doc_number] => 20080301525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'DATA REFRESH APPARATUS AND DATA REFRESH METHOD' [patent_app_type] => utility [patent_app_number] => 12/129754 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4862 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301525.pdf [firstpage_image] =>[orig_patent_app_number] => 12129754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129754
Data refresh apparatus and data refresh method May 29, 2008 Issued
Array ( [id] => 4700305 [patent_doc_number] => 20080222489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION' [patent_app_type] => utility [patent_app_number] => 12/127118 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1983 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222489.pdf [firstpage_image] =>[orig_patent_app_number] => 12127118 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127118
Apparatus for implementing processor bus speculative data completion May 26, 2008 Issued
Array ( [id] => 7993269 [patent_doc_number] => 08078943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Error correction code for correcting shift and additive errors' [patent_app_type] => utility [patent_app_number] => 12/126839 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3377 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078943.pdf [firstpage_image] =>[orig_patent_app_number] => 12126839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126839
Error correction code for correcting shift and additive errors May 22, 2008 Issued
Array ( [id] => 6006210 [patent_doc_number] => 20110119539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'PATTERN GENERATOR AND MEMORY TESTING DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/991876 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4823 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119539.pdf [firstpage_image] =>[orig_patent_app_number] => 12991876 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/991876
Pattern generator and memory testing device using the same May 20, 2008 Issued
Array ( [id] => 8343175 [patent_doc_number] => 08245113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Convolution-encoded RAID with trellis-decode-rebuild' [patent_app_type] => utility [patent_app_number] => 12/115455 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12115455 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115455
Convolution-encoded RAID with trellis-decode-rebuild May 4, 2008 Issued
Array ( [id] => 4815192 [patent_doc_number] => 20080195823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD AND APPARATUS FOR CONVOLUTIONAL INTERLEAVING/DE-INTERLEAVING TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 12/106535 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6894 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195823.pdf [firstpage_image] =>[orig_patent_app_number] => 12106535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106535
METHOD AND APPARATUS FOR CONVOLUTIONAL INTERLEAVING/DE-INTERLEAVING TECHNIQUE Apr 20, 2008 Abandoned
Array ( [id] => 6253310 [patent_doc_number] => 20100138718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'METHOD AND DEVICE FOR PADDING OPTIMIZATION OF SEGMENTED TURBO CODES' [patent_app_type] => utility [patent_app_number] => 12/450301 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6168 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138718.pdf [firstpage_image] =>[orig_patent_app_number] => 12450301 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/450301
Method and device for padding optimization of segmented turbo codes Mar 19, 2008 Issued
Array ( [id] => 4881999 [patent_doc_number] => 20080155382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'SYSTEM AND METHOD FOR IMPLEMENTING A REED SOLOMON MULTIPLICATION SECTION FROM EXCLUSIVE-OR LOGIC' [patent_app_type] => utility [patent_app_number] => 12/046049 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11616 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155382.pdf [firstpage_image] =>[orig_patent_app_number] => 12046049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/046049
System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic Mar 10, 2008 Issued
Array ( [id] => 58318 [patent_doc_number] => 07774682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Processing configuration data frames' [patent_app_type] => utility [patent_app_number] => 12/032448 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2883 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774682.pdf [firstpage_image] =>[orig_patent_app_number] => 12032448 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032448
Processing configuration data frames Feb 14, 2008 Issued
Array ( [id] => 5393455 [patent_doc_number] => 20090210768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'EXCEPTION CONDITION HANDLING AT A CHANNEL SUBSYSTEM IN AN I/O PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/030925 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11282 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210768.pdf [firstpage_image] =>[orig_patent_app_number] => 12030925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030925
Exception condition handling at a channel subsystem in an I/O processing system Feb 13, 2008 Issued
Array ( [id] => 7756645 [patent_doc_number] => 08112699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Error detecting/correcting scheme for memories' [patent_app_type] => utility [patent_app_number] => 12/031289 [patent_app_country] => US [patent_app_date] => 2008-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5485 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112699.pdf [firstpage_image] =>[orig_patent_app_number] => 12031289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031289
Error detecting/correcting scheme for memories Feb 13, 2008 Issued
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