Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 118374 [patent_doc_number] => 07716561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Multi-threshold reliability decoding of low-density parity check codes' [patent_app_type] => utility [patent_app_number] => 11/466292 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 12497 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716561.pdf [firstpage_image] =>[orig_patent_app_number] => 11466292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466292
Multi-threshold reliability decoding of low-density parity check codes Aug 21, 2006 Issued
Array ( [id] => 4996247 [patent_doc_number] => 20070011592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Decoder architecture for Reed Solomon codes' [patent_app_type] => utility [patent_app_number] => 11/505451 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6441 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011592.pdf [firstpage_image] =>[orig_patent_app_number] => 11505451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/505451
Decoder architecture for Reed Solomon codes Aug 16, 2006 Abandoned
Array ( [id] => 87885 [patent_doc_number] => 07743313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'System for impulse noise and radio frequency interference detection' [patent_app_type] => utility [patent_app_number] => 11/506052 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12590 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743313.pdf [firstpage_image] =>[orig_patent_app_number] => 11506052 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506052
System for impulse noise and radio frequency interference detection Aug 16, 2006 Issued
Array ( [id] => 4998819 [patent_doc_number] => 20070041453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Signal Processing Apparatus, Program Product and Method Therefor' [patent_app_type] => utility [patent_app_number] => 11/464941 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20070041453.pdf [firstpage_image] =>[orig_patent_app_number] => 11464941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464941
Signal processing apparatus and method therefor Aug 15, 2006 Issued
Array ( [id] => 4706434 [patent_doc_number] => 20080065958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications' [patent_app_type] => utility [patent_app_number] => 11/504158 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3119 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065958.pdf [firstpage_image] =>[orig_patent_app_number] => 11504158 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504158
Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications Aug 14, 2006 Issued
Array ( [id] => 97038 [patent_doc_number] => 07734987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Communication method and system using two or more coding schemes' [patent_app_type] => utility [patent_app_number] => 11/498753 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 8785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734987.pdf [firstpage_image] =>[orig_patent_app_number] => 11498753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498753
Communication method and system using two or more coding schemes Aug 3, 2006 Issued
Array ( [id] => 5001364 [patent_doc_number] => 20070043998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'SYSTEMS AND METHODS FOR A TURBO LOW-DENSITY PARITY-CHECK DECODER' [patent_app_type] => utility [patent_app_number] => 11/462241 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043998.pdf [firstpage_image] =>[orig_patent_app_number] => 11462241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462241
Systems and methods for a turbo low-density parity-check decoder Aug 2, 2006 Issued
Array ( [id] => 4735613 [patent_doc_number] => 20080052595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Methods and apparatus for low-density parity check decoding using hardware-sharing and serial sum-product architecture' [patent_app_type] => utility [patent_app_number] => 11/496121 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5964 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052595.pdf [firstpage_image] =>[orig_patent_app_number] => 11496121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/496121
Methods and apparatus for low-density parity check decoding using hardware-sharing and serial sum-product architecture Jul 30, 2006 Issued
Array ( [id] => 5001365 [patent_doc_number] => 20070043999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus' [patent_app_type] => utility [patent_app_number] => 11/495715 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 20464 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043999.pdf [firstpage_image] =>[orig_patent_app_number] => 11495715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495715
Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus Jul 30, 2006 Issued
Array ( [id] => 5467638 [patent_doc_number] => 20090327838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD FOR IT' [patent_app_type] => utility [patent_app_number] => 11/989383 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4064 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327838.pdf [firstpage_image] =>[orig_patent_app_number] => 11989383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/989383
MEMORY SYSTEM AND OPERATING METHOD FOR IT Jul 27, 2006 Abandoned
Array ( [id] => 5206664 [patent_doc_number] => 20070028146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Semiconductor memory device system, and method for operating a semiconductor memory device system' [patent_app_type] => utility [patent_app_number] => 11/495230 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028146.pdf [firstpage_image] =>[orig_patent_app_number] => 11495230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495230
Semiconductor memory device system, and method for operating a semiconductor memory device system Jul 27, 2006 Abandoned
Array ( [id] => 5156035 [patent_doc_number] => 20070038918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Data backup method and memory device' [patent_app_type] => utility [patent_app_number] => 11/493891 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4553 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038918.pdf [firstpage_image] =>[orig_patent_app_number] => 11493891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493891
Data backup method and memory device Jul 26, 2006 Issued
Array ( [id] => 5012734 [patent_doc_number] => 20070283213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Method and apparatus for self-compensation on belief-propagation algorithm' [patent_app_type] => utility [patent_app_number] => 11/492579 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2789 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283213.pdf [firstpage_image] =>[orig_patent_app_number] => 11492579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492579
Method and apparatus for self-compensation on belief-propagation algorithm Jul 24, 2006 Issued
Array ( [id] => 4590270 [patent_doc_number] => 07831895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Universal error control coding system for digital communication and data storage systems' [patent_app_type] => utility [patent_app_number] => 11/492383 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 29019 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831895.pdf [firstpage_image] =>[orig_patent_app_number] => 11492383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492383
Universal error control coding system for digital communication and data storage systems Jul 24, 2006 Issued
Array ( [id] => 5108826 [patent_doc_number] => 20070067704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Deinterleaver and dual-viterbi decoder architecture' [patent_app_type] => utility [patent_app_number] => 11/490844 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11724 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067704.pdf [firstpage_image] =>[orig_patent_app_number] => 11490844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490844
Deinterleaver and dual-viterbi decoder architecture Jul 20, 2006 Issued
Array ( [id] => 227051 [patent_doc_number] => 07607075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Method and apparatus for encoding and decoding data' [patent_app_type] => utility [patent_app_number] => 11/457903 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/607/07607075.pdf [firstpage_image] =>[orig_patent_app_number] => 11457903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/457903
Method and apparatus for encoding and decoding data Jul 16, 2006 Issued
Array ( [id] => 107947 [patent_doc_number] => 07725797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Buffer for storing data and forward error correction (FEC)' [patent_app_type] => utility [patent_app_number] => 11/482437 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8112 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725797.pdf [firstpage_image] =>[orig_patent_app_number] => 11482437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482437
Buffer for storing data and forward error correction (FEC) Jul 6, 2006 Issued
Array ( [id] => 4798996 [patent_doc_number] => 20080010582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'SYSTEM AND METHOD FOR VARIABLE FORWARD ERROR CORRECTION (FEC) PROTECTION' [patent_app_type] => utility [patent_app_number] => 11/428689 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4691 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010582.pdf [firstpage_image] =>[orig_patent_app_number] => 11428689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428689
System and method for variable forward error correction (FEC) protection Jul 4, 2006 Issued
Array ( [id] => 163416 [patent_doc_number] => 07676719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Transmitter apparatus and multiantenna transmitter apparatus' [patent_app_type] => utility [patent_app_number] => 11/994624 [patent_app_country] => US [patent_app_date] => 2006-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 53 [patent_no_of_words] => 11119 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676719.pdf [firstpage_image] =>[orig_patent_app_number] => 11994624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/994624
Transmitter apparatus and multiantenna transmitter apparatus Jul 3, 2006 Issued
Array ( [id] => 97037 [patent_doc_number] => 07734986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Write margin adjustment mechanism in a tape drive system' [patent_app_type] => utility [patent_app_number] => 11/479753 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734986.pdf [firstpage_image] =>[orig_patent_app_number] => 11479753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479753
Write margin adjustment mechanism in a tape drive system Jun 28, 2006 Issued
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