Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6211700
[patent_doc_number] => 20020073375
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[patent_kind] => A1
[patent_issue_date] => 2002-06-13
[patent_title] => 'Method and apparatus for test generation during circuit design'
[patent_app_type] => new
[patent_app_number] => 10/073461
[patent_app_country] => US
[patent_app_date] => 2002-02-11
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[pdf_file] => publications/A1/0073/20020073375.pdf
[firstpage_image] =>[orig_patent_app_number] => 10073461
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/073461 | Method and apparatus for test generation during circuit design | Feb 10, 2002 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'Method and apparatus for decoding error correction code'
[patent_app_type] => utility
[patent_app_number] => 10/468322
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[pdf_file] => patents/07/139/07139961.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/468322 | Method and apparatus for decoding error correction code | Feb 3, 2002 | Issued |
Array
(
[id] => 1043289
[patent_doc_number] => 06871316
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[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Delay reduction of hardware implementation of the maximum a posteriori (MAP) method'
[patent_app_type] => utility
[patent_app_number] => 10/060526
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[patent_app_date] => 2002-01-30
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[pdf_file] => patents/06/871/06871316.pdf
[firstpage_image] =>[orig_patent_app_number] => 10060526
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060526 | Delay reduction of hardware implementation of the maximum a posteriori (MAP) method | Jan 29, 2002 | Issued |
Array
(
[id] => 792833
[patent_doc_number] => 06986093
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[patent_issue_date] => 2006-01-10
[patent_title] => 'Apparatus for reproducing data and apparatus for recording/reproducing data'
[patent_app_type] => utility
[patent_app_number] => 10/060789
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060789 | Apparatus for reproducing data and apparatus for recording/reproducing data | Jan 29, 2002 | Issued |
Array
(
[id] => 965737
[patent_doc_number] => 06950976
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[patent_issue_date] => 2005-09-27
[patent_title] => 'Maximum likelihood decoding for input streams containing known data'
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[patent_app_date] => 2002-01-25
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[firstpage_image] =>[orig_patent_app_number] => 10058168
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/058168 | Maximum likelihood decoding for input streams containing known data | Jan 24, 2002 | Issued |
Array
(
[id] => 1025030
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[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Method and arrangement for decoding convolutionally encoded code word'
[patent_app_type] => utility
[patent_app_number] => 10/056399
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[firstpage_image] =>[orig_patent_app_number] => 10056399
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/056399 | Method and arrangement for decoding convolutionally encoded code word | Jan 22, 2002 | Issued |
Array
(
[id] => 933522
[patent_doc_number] => 06981197
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[patent_issue_date] => 2005-12-27
[patent_title] => 'Enhanced interleave type error correction method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/057831
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[patent_app_date] => 2002-01-23
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[pdf_file] => patents/06/981/06981197.pdf
[firstpage_image] =>[orig_patent_app_number] => 10057831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/057831 | Enhanced interleave type error correction method and apparatus | Jan 22, 2002 | Issued |
Array
(
[id] => 1043248
[patent_doc_number] => 06871301
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[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Apparatus and method for using a 2-wire bus to deskew 4 XAUI lanes across multiple ASIC chips'
[patent_app_type] => utility
[patent_app_number] => 10/053761
[patent_app_country] => US
[patent_app_date] => 2002-01-22
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[pdf_file] => patents/06/871/06871301.pdf
[firstpage_image] =>[orig_patent_app_number] => 10053761
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/053761 | Apparatus and method for using a 2-wire bus to deskew 4 XAUI lanes across multiple ASIC chips | Jan 21, 2002 | Issued |
Array
(
[id] => 7281089
[patent_doc_number] => 20040063466
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[patent_issue_date] => 2004-04-01
[patent_title] => 'Radio communication apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/466688 | Radio communication apparatus | Jan 21, 2002 | Issued |
Array
(
[id] => 6789060
[patent_doc_number] => 20030140299
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[patent_issue_date] => 2003-07-24
[patent_title] => 'Error detection in storage data'
[patent_app_type] => new
[patent_app_number] => 10/055593
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[patent_app_date] => 2002-01-22
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[firstpage_image] =>[orig_patent_app_number] => 10055593
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055593 | Error detection in storage data | Jan 21, 2002 | Issued |
Array
(
[id] => 5848571
[patent_doc_number] => 20020133780
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[patent_issue_date] => 2002-09-19
[patent_title] => 'Method and apparatus for protecting lossless transmission of a data stream'
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[pdf_file] => publications/A1/0133/20020133780.pdf
[firstpage_image] =>[orig_patent_app_number] => 10046991
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/046991 | Method and apparatus for protecting lossless transmission of a data stream | Jan 14, 2002 | Issued |
Array
(
[id] => 6857807
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[patent_title] => 'Method and apparatus for solving key equation polynomials in decoding error correction codes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/044670 | Method and apparatus for solving key equation polynomials in decoding error correction codes | Jan 10, 2002 | Abandoned |
Array
(
[id] => 6661161
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[patent_title] => 'Methods and apparatus for error detection and correction in an electronic shelf label system'
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Array
(
[id] => 7608033
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[patent_title] => 'Decoding low density parity check codes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/044624 | Decoding low density parity check codes | Jan 7, 2002 | Issued |
Array
(
[id] => 7618392
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[patent_title] => 'Skew adjusting circuit and semiconductor integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/013497 | Skew adjusting circuit and semiconductor integrated circuit | Dec 12, 2001 | Issued |
Array
(
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Array
(
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Array
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Array
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