Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6245529 [patent_doc_number] => 20020046374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Method of testing memory device, method of manufacturing memory device, apparatus for testing memory device, method of testing memory module, method of manufacturing memory module, apparatus for testing memory module and method of manufacturing computer' [patent_app_type] => new [patent_app_number] => 09/736282 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12999 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046374.pdf [firstpage_image] =>[orig_patent_app_number] => 09736282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736282
Method of testing memory device, method of manufacturing memory device, apparatus for testing memory device, method of testing memory module, method of manufacturing memory module, apparatus for testing memory module and method of manufacturing computer Dec 14, 2000 Abandoned
Array ( [id] => 6467949 [patent_doc_number] => 20020021721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Robust carrier identifying method and apparatus for bandwidth-on-demand (BOD) system' [patent_app_type] => new [patent_app_number] => 09/735675 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7039 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021721.pdf [firstpage_image] =>[orig_patent_app_number] => 09735675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735675
Robust carrier identifying method and apparatus for bandwidth-on-demand (BOD) system Dec 12, 2000 Issued
Array ( [id] => 1234595 [patent_doc_number] => 06697990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Interleaver design for parsed parallel concatenated codes' [patent_app_type] => B2 [patent_app_number] => 09/734841 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7381 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697990.pdf [firstpage_image] =>[orig_patent_app_number] => 09734841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734841
Interleaver design for parsed parallel concatenated codes Dec 12, 2000 Issued
Array ( [id] => 649128 [patent_doc_number] => 07120846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Data transmission device, data receiving device, data transfer device and method' [patent_app_type] => utility [patent_app_number] => 09/734702 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7573 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120846.pdf [firstpage_image] =>[orig_patent_app_number] => 09734702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734702
Data transmission device, data receiving device, data transfer device and method Dec 12, 2000 Issued
Array ( [id] => 1144141 [patent_doc_number] => 06785856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Internal self-test circuit for a memory array' [patent_app_type] => B1 [patent_app_number] => 09/732616 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2294 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785856.pdf [firstpage_image] =>[orig_patent_app_number] => 09732616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/732616
Internal self-test circuit for a memory array Dec 6, 2000 Issued
Array ( [id] => 6211714 [patent_doc_number] => 20020073377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Ameliorating the adverse impact of burst errors on the operation of ISI detectors' [patent_app_type] => new [patent_app_number] => 09/732822 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2205 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073377.pdf [firstpage_image] =>[orig_patent_app_number] => 09732822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/732822
Ameliorating the adverse impact of burst errors on the operation of ISI detectors Dec 6, 2000 Issued
Array ( [id] => 1243228 [patent_doc_number] => 06684353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Reliability monitor for a memory array' [patent_app_type] => B1 [patent_app_number] => 09/733252 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2200 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684353.pdf [firstpage_image] =>[orig_patent_app_number] => 09733252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733252
Reliability monitor for a memory array Dec 6, 2000 Issued
Array ( [id] => 6948349 [patent_doc_number] => 20010021986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'High dynamic range error rate monitor' [patent_app_type] => new [patent_app_number] => 09/731243 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4477 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021986.pdf [firstpage_image] =>[orig_patent_app_number] => 09731243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731243
High dynamic range error rate monitor Dec 5, 2000 Issued
Array ( [id] => 1088780 [patent_doc_number] => 06832348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Semiconductor integrated circuit having self-diagnosis test function and test method thereof' [patent_app_type] => B2 [patent_app_number] => 09/730817 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3079 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832348.pdf [firstpage_image] =>[orig_patent_app_number] => 09730817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730817
Semiconductor integrated circuit having self-diagnosis test function and test method thereof Dec 5, 2000 Issued
Array ( [id] => 1059044 [patent_doc_number] => 06857088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Method and system for testing the logic of a complex digital circuit containing embedded memory arrays' [patent_app_type] => utility [patent_app_number] => 09/732487 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4143 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857088.pdf [firstpage_image] =>[orig_patent_app_number] => 09732487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/732487
Method and system for testing the logic of a complex digital circuit containing embedded memory arrays Dec 5, 2000 Issued
Array ( [id] => 5830562 [patent_doc_number] => 20020069383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Method for testing a memory array' [patent_app_type] => new [patent_app_number] => 09/731687 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4521 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069383.pdf [firstpage_image] =>[orig_patent_app_number] => 09731687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731687
Method for testing a memory array Dec 4, 2000 Issued
Array ( [id] => 7642325 [patent_doc_number] => 06430721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for decreasing the frame error rate in data transmission in the form of data frames' [patent_app_type] => B2 [patent_app_number] => 09/730288 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430721.pdf [firstpage_image] =>[orig_patent_app_number] => 09730288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730288
Method for decreasing the frame error rate in data transmission in the form of data frames Dec 4, 2000 Issued
Array ( [id] => 1186730 [patent_doc_number] => 06738937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method for nondisruptive testing of device and host attachment to storage subsystems' [patent_app_type] => B1 [patent_app_number] => 09/728415 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738937.pdf [firstpage_image] =>[orig_patent_app_number] => 09728415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/728415
Method for nondisruptive testing of device and host attachment to storage subsystems Nov 30, 2000 Issued
09/693809 Command-driven test modes Oct 19, 2000 Abandoned
Array ( [id] => 1272117 [patent_doc_number] => 06662326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Circuit cell having a built-in self-test function, and test method therefor' [patent_app_type] => B1 [patent_app_number] => 09/686834 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4554 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662326.pdf [firstpage_image] =>[orig_patent_app_number] => 09686834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686834
Circuit cell having a built-in self-test function, and test method therefor Oct 10, 2000 Issued
Array ( [id] => 1280013 [patent_doc_number] => 06654926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Soft decision maximum likelihood encoder and decoder' [patent_app_type] => B1 [patent_app_number] => 09/686237 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13007 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654926.pdf [firstpage_image] =>[orig_patent_app_number] => 09686237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686237
Soft decision maximum likelihood encoder and decoder Oct 10, 2000 Issued
Array ( [id] => 7962129 [patent_doc_number] => 06681365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method and apparatus for providing channel error protection for a source coded bit stream' [patent_app_type] => B1 [patent_app_number] => 09/680708 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4390 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681365.pdf [firstpage_image] =>[orig_patent_app_number] => 09680708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680708
Method and apparatus for providing channel error protection for a source coded bit stream Oct 5, 2000 Issued
Array ( [id] => 7633001 [patent_doc_number] => 06658619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Systems and methods for implementing hierarchical acknowledgement bitmaps in an ARQ protocol' [patent_app_type] => B1 [patent_app_number] => 09/679286 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4225 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658619.pdf [firstpage_image] =>[orig_patent_app_number] => 09679286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679286
Systems and methods for implementing hierarchical acknowledgement bitmaps in an ARQ protocol Oct 5, 2000 Issued
Array ( [id] => 1250304 [patent_doc_number] => 06675328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'System and method to determine data throughput in a communication network' [patent_app_type] => B1 [patent_app_number] => 09/684453 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7123 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675328.pdf [firstpage_image] =>[orig_patent_app_number] => 09684453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684453
System and method to determine data throughput in a communication network Oct 5, 2000 Issued
Array ( [id] => 1258622 [patent_doc_number] => 06671841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method for on-line circuit debug using JTAG and shadow scan in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/680237 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5977 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671841.pdf [firstpage_image] =>[orig_patent_app_number] => 09680237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680237
Method for on-line circuit debug using JTAG and shadow scan in a microprocessor Oct 4, 2000 Issued
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