Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1066851
[patent_doc_number] => 06851076
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-01
[patent_title] => 'Memory tester has memory sets configurable for use as error catch RAM, Tag RAM\'s, buffer memories and stimulus log RAM'
[patent_app_type] => utility
[patent_app_number] => 09/672650
[patent_app_country] => US
[patent_app_date] => 2000-09-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/851/06851076.pdf
[firstpage_image] =>[orig_patent_app_number] => 09672650
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/672650 | Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM | Sep 27, 2000 | Issued |
Array
(
[id] => 1553882
[patent_doc_number] => 06347388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Method and apparatus for test generation during circuit design'
[patent_app_type] => B1
[patent_app_number] => 09/668001
[patent_app_country] => US
[patent_app_date] => 2000-09-21
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/347/06347388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09668001
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/668001 | Method and apparatus for test generation during circuit design | Sep 20, 2000 | Issued |
Array
(
[id] => 1279948
[patent_doc_number] => 06654917
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-25
[patent_title] => 'Method and apparatus for scanning free-running logic'
[patent_app_type] => B1
[patent_app_number] => 09/657106
[patent_app_country] => US
[patent_app_date] => 2000-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/657106 | Method and apparatus for scanning free-running logic | Sep 6, 2000 | Issued |
Array
(
[id] => 1258664
[patent_doc_number] => 06671852
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-30
[patent_title] => 'Syndrome assisted iterative decoder for turbo codes'
[patent_app_type] => B1
[patent_app_number] => 09/655996
[patent_app_country] => US
[patent_app_date] => 2000-09-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/671/06671852.pdf
[firstpage_image] =>[orig_patent_app_number] => 09655996
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/655996 | Syndrome assisted iterative decoder for turbo codes | Sep 5, 2000 | Issued |
Array
(
[id] => 1362191
[patent_doc_number] => 06587982
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[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling'
[patent_app_type] => B1
[patent_app_number] => 09/654965
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[pdf_file] => patents/06/587/06587982.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654965 | Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling | Sep 4, 2000 | Issued |
Array
(
[id] => 1329456
[patent_doc_number] => 06606726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-12
[patent_title] => 'Optimization of acceptance of erroneous codewords and throughput'
[patent_app_type] => B1
[patent_app_number] => 09/654779
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[firstpage_image] =>[orig_patent_app_number] => 09654779
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654779 | Optimization of acceptance of erroneous codewords and throughput | Sep 4, 2000 | Issued |
Array
(
[id] => 1325856
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[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Low power path memory for viterbi decoders'
[patent_app_type] => B1
[patent_app_number] => 09/654331
[patent_app_country] => US
[patent_app_date] => 2000-09-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/615/06615388.pdf
[firstpage_image] =>[orig_patent_app_number] => 09654331
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654331 | Low power path memory for viterbi decoders | Aug 31, 2000 | Issued |
Array
(
[id] => 1327132
[patent_doc_number] => 06609222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-19
[patent_title] => 'Methods and circuitry for built-in self-testing of content addressable memories'
[patent_app_type] => B1
[patent_app_number] => 09/654197
[patent_app_country] => US
[patent_app_date] => 2000-09-01
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 9035
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[pdf_file] => patents/06/609/06609222.pdf
[firstpage_image] =>[orig_patent_app_number] => 09654197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654197 | Methods and circuitry for built-in self-testing of content addressable memories | Aug 31, 2000 | Issued |
Array
(
[id] => 1311867
[patent_doc_number] => 06625778
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Turbo error-correcting decoder and turbo error-correcting decoding method'
[patent_app_type] => B1
[patent_app_number] => 09/654067
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[pdf_file] => patents/06/625/06625778.pdf
[firstpage_image] =>[orig_patent_app_number] => 09654067
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654067 | Turbo error-correcting decoder and turbo error-correcting decoding method | Aug 31, 2000 | Issued |
Array
(
[id] => 1324326
[patent_doc_number] => 06611935
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-26
[patent_title] => 'Method and system for efficiently testing circuitry'
[patent_app_type] => B1
[patent_app_number] => 09/652806
[patent_app_country] => US
[patent_app_date] => 2000-08-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652806 | Method and system for efficiently testing circuitry | Aug 30, 2000 | Issued |
Array
(
[id] => 1314863
[patent_doc_number] => 06622271
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[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'Method and apparatus for operating a system to test integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/652888
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[pdf_file] => patents/06/622/06622271.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652888 | Method and apparatus for operating a system to test integrated circuits | Aug 30, 2000 | Issued |
Array
(
[id] => 1284996
[patent_doc_number] => 06651212
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory'
[patent_app_type] => B1
[patent_app_number] => 09/653586
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/653586 | Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory | Aug 30, 2000 | Issued |
Array
(
[id] => 1093007
[patent_doc_number] => 06829737
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[patent_issue_date] => 2004-12-07
[patent_title] => 'Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results'
[patent_app_type] => B1
[patent_app_number] => 09/651858
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Array
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[patent_title] => 'Reconfigurable built-in self-test engine for testing a reconfigurable memory'
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Array
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[patent_title] => 'Hardware circuitry to speed testing of the contents of a memory'
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Array
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[patent_title] => 'Error propagation control method in decision feedback equalization and magnetic recording/reproducing device'
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Array
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[patent_issue_date] => 2001-11-20
[patent_title] => 'System including a ferroelectric memory'
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Array
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Array
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[patent_title] => 'Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same'
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Array
(
[id] => 4412821
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[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Code image data output apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 9/566016
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 566016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/566016 | Code image data output apparatus and method | May 4, 2000 | Issued |