Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1066851 [patent_doc_number] => 06851076 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Memory tester has memory sets configurable for use as error catch RAM, Tag RAM\'s, buffer memories and stimulus log RAM' [patent_app_type] => utility [patent_app_number] => 09/672650 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18892 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851076.pdf [firstpage_image] =>[orig_patent_app_number] => 09672650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672650
Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM Sep 27, 2000 Issued
Array ( [id] => 1553882 [patent_doc_number] => 06347388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method and apparatus for test generation during circuit design' [patent_app_type] => B1 [patent_app_number] => 09/668001 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11636 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347388.pdf [firstpage_image] =>[orig_patent_app_number] => 09668001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668001
Method and apparatus for test generation during circuit design Sep 20, 2000 Issued
Array ( [id] => 1279948 [patent_doc_number] => 06654917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method and apparatus for scanning free-running logic' [patent_app_type] => B1 [patent_app_number] => 09/657106 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4327 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654917.pdf [firstpage_image] =>[orig_patent_app_number] => 09657106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657106
Method and apparatus for scanning free-running logic Sep 6, 2000 Issued
Array ( [id] => 1258664 [patent_doc_number] => 06671852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Syndrome assisted iterative decoder for turbo codes' [patent_app_type] => B1 [patent_app_number] => 09/655996 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4669 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671852.pdf [firstpage_image] =>[orig_patent_app_number] => 09655996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655996
Syndrome assisted iterative decoder for turbo codes Sep 5, 2000 Issued
Array ( [id] => 1362191 [patent_doc_number] => 06587982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling' [patent_app_type] => B1 [patent_app_number] => 09/654965 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3491 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587982.pdf [firstpage_image] =>[orig_patent_app_number] => 09654965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654965
Method of micro-architectural implementation of interface between bist state machine and tester interface to enable bist cycling Sep 4, 2000 Issued
Array ( [id] => 1329456 [patent_doc_number] => 06606726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Optimization of acceptance of erroneous codewords and throughput' [patent_app_type] => B1 [patent_app_number] => 09/654779 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606726.pdf [firstpage_image] =>[orig_patent_app_number] => 09654779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654779
Optimization of acceptance of erroneous codewords and throughput Sep 4, 2000 Issued
Array ( [id] => 1325856 [patent_doc_number] => 06615388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Low power path memory for viterbi decoders' [patent_app_type] => B1 [patent_app_number] => 09/654331 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 5108 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615388.pdf [firstpage_image] =>[orig_patent_app_number] => 09654331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654331
Low power path memory for viterbi decoders Aug 31, 2000 Issued
Array ( [id] => 1327132 [patent_doc_number] => 06609222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Methods and circuitry for built-in self-testing of content addressable memories' [patent_app_type] => B1 [patent_app_number] => 09/654197 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 9035 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609222.pdf [firstpage_image] =>[orig_patent_app_number] => 09654197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654197
Methods and circuitry for built-in self-testing of content addressable memories Aug 31, 2000 Issued
Array ( [id] => 1311867 [patent_doc_number] => 06625778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Turbo error-correcting decoder and turbo error-correcting decoding method' [patent_app_type] => B1 [patent_app_number] => 09/654067 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5505 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625778.pdf [firstpage_image] =>[orig_patent_app_number] => 09654067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654067
Turbo error-correcting decoder and turbo error-correcting decoding method Aug 31, 2000 Issued
Array ( [id] => 1324326 [patent_doc_number] => 06611935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Method and system for efficiently testing circuitry' [patent_app_type] => B1 [patent_app_number] => 09/652806 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5875 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611935.pdf [firstpage_image] =>[orig_patent_app_number] => 09652806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652806
Method and system for efficiently testing circuitry Aug 30, 2000 Issued
Array ( [id] => 1314863 [patent_doc_number] => 06622271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method and apparatus for operating a system to test integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/652888 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7703 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622271.pdf [firstpage_image] =>[orig_patent_app_number] => 09652888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652888
Method and apparatus for operating a system to test integrated circuits Aug 30, 2000 Issued
Array ( [id] => 1284996 [patent_doc_number] => 06651212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/653586 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 11552 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651212.pdf [firstpage_image] =>[orig_patent_app_number] => 09653586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653586
Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory Aug 30, 2000 Issued
Array ( [id] => 1093007 [patent_doc_number] => 06829737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results' [patent_app_type] => B1 [patent_app_number] => 09/651858 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6868 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829737.pdf [firstpage_image] =>[orig_patent_app_number] => 09651858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651858
Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results Aug 29, 2000 Issued
Array ( [id] => 7625686 [patent_doc_number] => 06769081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Reconfigurable built-in self-test engine for testing a reconfigurable memory' [patent_app_type] => B1 [patent_app_number] => 09/651359 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10452 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769081.pdf [firstpage_image] =>[orig_patent_app_number] => 09651359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651359
Reconfigurable built-in self-test engine for testing a reconfigurable memory Aug 29, 2000 Issued
Array ( [id] => 1295209 [patent_doc_number] => 06640320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Hardware circuitry to speed testing of the contents of a memory' [patent_app_type] => B1 [patent_app_number] => 09/651533 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4375 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640320.pdf [firstpage_image] =>[orig_patent_app_number] => 09651533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651533
Hardware circuitry to speed testing of the contents of a memory Aug 28, 2000 Issued
Array ( [id] => 1337654 [patent_doc_number] => 06604221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Error propagation control method in decision feedback equalization and magnetic recording/reproducing device' [patent_app_type] => B1 [patent_app_number] => 09/628035 [patent_app_country] => US [patent_app_date] => 2000-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 7483 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604221.pdf [firstpage_image] =>[orig_patent_app_number] => 09628035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628035
Error propagation control method in decision feedback equalization and magnetic recording/reproducing device Jul 26, 2000 Issued
Array ( [id] => 4350501 [patent_doc_number] => 06321360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'System including a ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 9/580180 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7073 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321360.pdf [firstpage_image] =>[orig_patent_app_number] => 580180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580180
System including a ferroelectric memory May 25, 2000 Issued
Array ( [id] => 1481367 [patent_doc_number] => 06389570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same' [patent_app_type] => B1 [patent_app_number] => 09/576973 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7246 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389570.pdf [firstpage_image] =>[orig_patent_app_number] => 09576973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576973
Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same May 23, 2000 Issued
Array ( [id] => 1162077 [patent_doc_number] => 06775803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same' [patent_app_type] => B1 [patent_app_number] => 09/576974 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7256 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775803.pdf [firstpage_image] =>[orig_patent_app_number] => 09576974 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576974
Recording medium for storing real time recording/reproduction information, method and apparatus for recording and reproducing in real time, and file operating method using the same May 23, 2000 Issued
Array ( [id] => 4412821 [patent_doc_number] => 06298460 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Code image data output apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/566016 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 89 [patent_no_of_words] => 29233 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298460.pdf [firstpage_image] =>[orig_patent_app_number] => 566016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566016
Code image data output apparatus and method May 4, 2000 Issued
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