Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1225977 [patent_doc_number] => 06704903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Simplified branch metric and method' [patent_app_type] => B1 [patent_app_number] => 09/507510 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3411 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704903.pdf [firstpage_image] =>[orig_patent_app_number] => 09507510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507510
Simplified branch metric and method Feb 17, 2000 Issued
Array ( [id] => 1407595 [patent_doc_number] => 06560730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for testing a non-volatile memory array having a low number of output pins' [patent_app_type] => B1 [patent_app_number] => 09/507234 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1350 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560730.pdf [firstpage_image] =>[orig_patent_app_number] => 09507234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507234
Method and apparatus for testing a non-volatile memory array having a low number of output pins Feb 17, 2000 Issued
Array ( [id] => 1348825 [patent_doc_number] => 06598204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'System and method of turbo decoding' [patent_app_type] => B1 [patent_app_number] => 09/507545 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 13311 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598204.pdf [firstpage_image] =>[orig_patent_app_number] => 09507545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507545
System and method of turbo decoding Feb 17, 2000 Issued
Array ( [id] => 1396314 [patent_doc_number] => 06567939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Merged data line test circuit for classifying and testing a plurality of data lines, and test method performed by the same' [patent_app_type] => B1 [patent_app_number] => 09/507764 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4203 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567939.pdf [firstpage_image] =>[orig_patent_app_number] => 09507764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507764
Merged data line test circuit for classifying and testing a plurality of data lines, and test method performed by the same Feb 17, 2000 Issued
Array ( [id] => 1580536 [patent_doc_number] => 06470471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Data error correction apparatus' [patent_app_type] => B1 [patent_app_number] => 09/506319 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3364 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470471.pdf [firstpage_image] =>[orig_patent_app_number] => 09506319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506319
Data error correction apparatus Feb 17, 2000 Issued
Array ( [id] => 1337602 [patent_doc_number] => 06604216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Telecommunications system and method for supporting an incremental redundancy error handling scheme using available gross rate channels' [patent_app_type] => B1 [patent_app_number] => 09/505792 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5626 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604216.pdf [firstpage_image] =>[orig_patent_app_number] => 09505792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505792
Telecommunications system and method for supporting an incremental redundancy error handling scheme using available gross rate channels Feb 16, 2000 Issued
Array ( [id] => 1444205 [patent_doc_number] => 06496954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Viterbi decoder and viterbi decoding method' [patent_app_type] => B1 [patent_app_number] => 09/505896 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8104 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496954.pdf [firstpage_image] =>[orig_patent_app_number] => 09505896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505896
Viterbi decoder and viterbi decoding method Feb 16, 2000 Issued
Array ( [id] => 1416457 [patent_doc_number] => 06550034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Built-in self test for content addressable memory' [patent_app_type] => B1 [patent_app_number] => 09/505549 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550034.pdf [firstpage_image] =>[orig_patent_app_number] => 09505549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505549
Built-in self test for content addressable memory Feb 16, 2000 Issued
Array ( [id] => 1407717 [patent_doc_number] => 06560737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for adding scan controllability and observability to domino CMOS with low area and delay overhead' [patent_app_type] => B1 [patent_app_number] => 09/505383 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2965 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560737.pdf [firstpage_image] =>[orig_patent_app_number] => 09505383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505383
Method for adding scan controllability and observability to domino CMOS with low area and delay overhead Feb 15, 2000 Issued
Array ( [id] => 1416446 [patent_doc_number] => 06550033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method and apparatus for exercising external memory with a memory built-in test' [patent_app_type] => B1 [patent_app_number] => 09/504907 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550033.pdf [firstpage_image] =>[orig_patent_app_number] => 09504907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504907
Method and apparatus for exercising external memory with a memory built-in test Feb 15, 2000 Issued
Array ( [id] => 1325768 [patent_doc_number] => 06615378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method and apparatus for holding failing information of a memory built-in self-test' [patent_app_type] => B1 [patent_app_number] => 09/504899 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6058 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615378.pdf [firstpage_image] =>[orig_patent_app_number] => 09504899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504899
Method and apparatus for holding failing information of a memory built-in self-test Feb 15, 2000 Issued
Array ( [id] => 1419480 [patent_doc_number] => 06546515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method of encoding a signal' [patent_app_type] => B1 [patent_app_number] => 09/505197 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5932 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546515.pdf [firstpage_image] =>[orig_patent_app_number] => 09505197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505197
Method of encoding a signal Feb 15, 2000 Issued
Array ( [id] => 1472125 [patent_doc_number] => 06460160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Chase iteration processing for decoding input data' [patent_app_type] => B1 [patent_app_number] => 09/503761 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4431 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460160.pdf [firstpage_image] =>[orig_patent_app_number] => 09503761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503761
Chase iteration processing for decoding input data Feb 13, 2000 Issued
Array ( [id] => 1365838 [patent_doc_number] => 06581178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Error correction coding/decoding method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/500845 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 9720 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581178.pdf [firstpage_image] =>[orig_patent_app_number] => 09500845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500845
Error correction coding/decoding method and apparatus Feb 9, 2000 Issued
Array ( [id] => 1485210 [patent_doc_number] => 06453439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Pseudo product code encoding and decoding apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/501613 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10420 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453439.pdf [firstpage_image] =>[orig_patent_app_number] => 09501613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501613
Pseudo product code encoding and decoding apparatus and method Feb 9, 2000 Issued
Array ( [id] => 1410391 [patent_doc_number] => 06557138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method for correction of errors in a binary word stored in multi-level memory cells, with minimum number of correction bits' [patent_app_type] => B1 [patent_app_number] => 09/500707 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7283 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557138.pdf [firstpage_image] =>[orig_patent_app_number] => 09500707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500707
Method for correction of errors in a binary word stored in multi-level memory cells, with minimum number of correction bits Feb 8, 2000 Issued
Array ( [id] => 1377897 [patent_doc_number] => 06578171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Method of correcting residual errors at the output of a turbodecoder' [patent_app_type] => B1 [patent_app_number] => 09/500425 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5402 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578171.pdf [firstpage_image] =>[orig_patent_app_number] => 09500425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500425
Method of correcting residual errors at the output of a turbodecoder Feb 8, 2000 Issued
Array ( [id] => 1431197 [patent_doc_number] => 06507927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method and device for estimating the reliability of a decoded symbol sequence' [patent_app_type] => B1 [patent_app_number] => 09/500170 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6095 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507927.pdf [firstpage_image] =>[orig_patent_app_number] => 09500170 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500170
Method and device for estimating the reliability of a decoded symbol sequence Feb 7, 2000 Issued
Array ( [id] => 1429792 [patent_doc_number] => 06530060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Sampled amplitude read channel employing a post processor with a boundary error compensator which compensates for boundary error events in a split-field data sector' [patent_app_type] => B1 [patent_app_number] => 09/499888 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9141 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530060.pdf [firstpage_image] =>[orig_patent_app_number] => 09499888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499888
Sampled amplitude read channel employing a post processor with a boundary error compensator which compensates for boundary error events in a split-field data sector Feb 7, 2000 Issued
Array ( [id] => 1432004 [patent_doc_number] => 06516443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Error detection convolution code and post processor for correcting dominant error events of a trellis sequence detector in a sampled amplitude read channel for disk storage systems' [patent_app_type] => B1 [patent_app_number] => 09/499930 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 25903 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516443.pdf [firstpage_image] =>[orig_patent_app_number] => 09499930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499930
Error detection convolution code and post processor for correcting dominant error events of a trellis sequence detector in a sampled amplitude read channel for disk storage systems Feb 7, 2000 Issued
Menu