Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7621090
[patent_doc_number] => 06978412
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-20
[patent_title] => 'Method and apparatus for adaptive frame tracking'
[patent_app_type] => utility
[patent_app_number] => 09/375120
[patent_app_country] => US
[patent_app_date] => 1999-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4640
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/978/06978412.pdf
[firstpage_image] =>[orig_patent_app_number] => 09375120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375120 | Method and apparatus for adaptive frame tracking | Aug 15, 1999 | Issued |
Array
(
[id] => 4311058
[patent_doc_number] => 06212662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Method and devices for the transmission of data with transmission error checking'
[patent_app_type] => 1
[patent_app_number] => 9/360632
[patent_app_country] => US
[patent_app_date] => 1999-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3696
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/212/06212662.pdf
[firstpage_image] =>[orig_patent_app_number] => 360632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/360632 | Method and devices for the transmission of data with transmission error checking | Jul 25, 1999 | Issued |
Array
(
[id] => 1419414
[patent_doc_number] => 06546510
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Burn-in mode detect circuit for semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/351384
[patent_app_country] => US
[patent_app_date] => 1999-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/546/06546510.pdf
[firstpage_image] =>[orig_patent_app_number] => 09351384
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351384 | Burn-in mode detect circuit for semiconductor device | Jul 12, 1999 | Issued |
Array
(
[id] => 7634952
[patent_doc_number] => 06381714
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Error detection method, error detection apparatus, and network system'
[patent_app_type] => B1
[patent_app_number] => 09/350888
[patent_app_country] => US
[patent_app_date] => 1999-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4453
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/381/06381714.pdf
[firstpage_image] =>[orig_patent_app_number] => 09350888
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350888 | Error detection method, error detection apparatus, and network system | Jul 11, 1999 | Issued |
Array
(
[id] => 1495498
[patent_doc_number] => 06418549
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Data transmission using arithmetic coding based continuous error detection'
[patent_app_type] => B1
[patent_app_number] => 09/351631
[patent_app_country] => US
[patent_app_date] => 1999-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7348
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/418/06418549.pdf
[firstpage_image] =>[orig_patent_app_number] => 09351631
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351631 | Data transmission using arithmetic coding based continuous error detection | Jul 11, 1999 | Issued |
Array
(
[id] => 1495482
[patent_doc_number] => 06418546
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Circuit for checking a tristate detection circuit'
[patent_app_type] => B1
[patent_app_number] => 09/351097
[patent_app_country] => US
[patent_app_date] => 1999-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3989
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/418/06418546.pdf
[firstpage_image] =>[orig_patent_app_number] => 09351097
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351097 | Circuit for checking a tristate detection circuit | Jul 8, 1999 | Issued |
Array
(
[id] => 1557724
[patent_doc_number] => 06401226
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Electronic system with self-test function and simulation circuit for electronic system'
[patent_app_type] => B1
[patent_app_number] => 09/348839
[patent_app_country] => US
[patent_app_date] => 1999-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 27
[patent_no_of_words] => 9260
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/401/06401226.pdf
[firstpage_image] =>[orig_patent_app_number] => 09348839
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348839 | Electronic system with self-test function and simulation circuit for electronic system | Jul 7, 1999 | Issued |
Array
(
[id] => 5877038
[patent_doc_number] => 20020049946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING OPERATION TEST AT HIGH SPEED WHILE REDUCING BURDEN ON TESTER'
[patent_app_type] => new
[patent_app_number] => 09/349260
[patent_app_country] => US
[patent_app_date] => 1999-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10569
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20020049946.pdf
[firstpage_image] =>[orig_patent_app_number] => 09349260
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/349260 | Synchronous semiconductor memory device capable of performing operation test at high speed while reducing burden on tester | Jul 7, 1999 | Issued |
Array
(
[id] => 1466518
[patent_doc_number] => 06393599
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Multi-chip data detector implementation for symmetric differential phase shift keying modulation formats'
[patent_app_type] => B1
[patent_app_number] => 09/347873
[patent_app_country] => US
[patent_app_date] => 1999-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 8481
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/393/06393599.pdf
[firstpage_image] =>[orig_patent_app_number] => 09347873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347873 | Multi-chip data detector implementation for symmetric differential phase shift keying modulation formats | Jul 5, 1999 | Issued |
Array
(
[id] => 1475171
[patent_doc_number] => 06408419
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-18
[patent_title] => 'Trellis code for extended partial response maximum likelihood (EPRML) channel'
[patent_app_type] => B1
[patent_app_number] => 09/347598
[patent_app_country] => US
[patent_app_date] => 1999-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 4701
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/408/06408419.pdf
[firstpage_image] =>[orig_patent_app_number] => 09347598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/347598 | Trellis code for extended partial response maximum likelihood (EPRML) channel | Jun 30, 1999 | Issued |
Array
(
[id] => 1485199
[patent_doc_number] => 06453437
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation'
[patent_app_type] => B1
[patent_app_number] => 09/348712
[patent_app_country] => US
[patent_app_date] => 1999-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6857
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/453/06453437.pdf
[firstpage_image] =>[orig_patent_app_number] => 09348712
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348712 | Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation | Jun 30, 1999 | Issued |
Array
(
[id] => 999203
[patent_doc_number] => 06915475
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-07-05
[patent_title] => 'Data integrity management for data storage systems'
[patent_app_type] => utility
[patent_app_number] => 09/342955
[patent_app_country] => US
[patent_app_date] => 1999-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3690
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/915/06915475.pdf
[firstpage_image] =>[orig_patent_app_number] => 09342955
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342955 | Data integrity management for data storage systems | Jun 28, 1999 | Issued |
Array
(
[id] => 1481327
[patent_doc_number] => 06389563
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Semiconductor memory test circuit and method for the same'
[patent_app_type] => B1
[patent_app_number] => 09/340731
[patent_app_country] => US
[patent_app_date] => 1999-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4090
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/389/06389563.pdf
[firstpage_image] =>[orig_patent_app_number] => 09340731
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340731 | Semiconductor memory test circuit and method for the same | Jun 28, 1999 | Issued |
Array
(
[id] => 1481382
[patent_doc_number] => 06389573
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Enhanced read retrial scheme'
[patent_app_type] => B1
[patent_app_number] => 09/343111
[patent_app_country] => US
[patent_app_date] => 1999-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3104
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/389/06389573.pdf
[firstpage_image] =>[orig_patent_app_number] => 09343111
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/343111 | Enhanced read retrial scheme | Jun 28, 1999 | Issued |
Array
(
[id] => 1475161
[patent_doc_number] => 06408416
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-18
[patent_title] => 'Data writing to data storage medium'
[patent_app_type] => B1
[patent_app_number] => 09/335312
[patent_app_country] => US
[patent_app_date] => 1999-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5752
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/408/06408416.pdf
[firstpage_image] =>[orig_patent_app_number] => 09335312
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/335312 | Data writing to data storage medium | Jun 15, 1999 | Issued |
Array
(
[id] => 1533331
[patent_doc_number] => 06480982
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Computer RAM memory system with enhanced scrubbing and sparing'
[patent_app_type] => B1
[patent_app_number] => 09/325814
[patent_app_country] => US
[patent_app_date] => 1999-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4872
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/480/06480982.pdf
[firstpage_image] =>[orig_patent_app_number] => 09325814
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/325814 | Computer RAM memory system with enhanced scrubbing and sparing | Jun 3, 1999 | Issued |
Array
(
[id] => 1602147
[patent_doc_number] => 06385752
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Method and apparatus for puncturing a convolutionally encoded bit stream'
[patent_app_type] => B1
[patent_app_number] => 09/323012
[patent_app_country] => US
[patent_app_date] => 1999-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2708
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385752.pdf
[firstpage_image] =>[orig_patent_app_number] => 09323012
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/323012 | Method and apparatus for puncturing a convolutionally encoded bit stream | May 31, 1999 | Issued |
Array
(
[id] => 7638563
[patent_doc_number] => 06397358
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Method of identifying a frame for erasure in a digital data transmission system'
[patent_app_type] => B1
[patent_app_number] => 09/322812
[patent_app_country] => US
[patent_app_date] => 1999-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2444
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/397/06397358.pdf
[firstpage_image] =>[orig_patent_app_number] => 09322812
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/322812 | Method of identifying a frame for erasure in a digital data transmission system | May 27, 1999 | Issued |
Array
(
[id] => 1572630
[patent_doc_number] => 06378106
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Viterbi decoding using single-wrong-turn correction'
[patent_app_type] => B1
[patent_app_number] => 09/321794
[patent_app_country] => US
[patent_app_date] => 1999-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 3449
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/378/06378106.pdf
[firstpage_image] =>[orig_patent_app_number] => 09321794
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/321794 | Viterbi decoding using single-wrong-turn correction | May 27, 1999 | Issued |
Array
(
[id] => 7642322
[patent_doc_number] => 06430724
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Soft selection combining based on successive erasures of frequency band components in a communication system'
[patent_app_type] => B1
[patent_app_number] => 09/322848
[patent_app_country] => US
[patent_app_date] => 1999-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5100
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/430/06430724.pdf
[firstpage_image] =>[orig_patent_app_number] => 09322848
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/322848 | Soft selection combining based on successive erasures of frequency band components in a communication system | May 27, 1999 | Issued |