Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1497947 [patent_doc_number] => 06343368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and system for fast maximum a posteriori decoding' [patent_app_type] => B1 [patent_app_number] => 09/252028 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5818 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343368.pdf [firstpage_image] =>[orig_patent_app_number] => 09252028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252028
Method and system for fast maximum a posteriori decoding Feb 17, 1999 Issued
Array ( [id] => 1604534 [patent_doc_number] => 06434720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of checking data integrity for a RAID 1 system' [patent_app_type] => B1 [patent_app_number] => 09/251954 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434720.pdf [firstpage_image] =>[orig_patent_app_number] => 09251954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251954
Method of checking data integrity for a RAID 1 system Feb 16, 1999 Issued
Array ( [id] => 1549800 [patent_doc_number] => 06374379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment' [patent_app_type] => B1 [patent_app_number] => 09/245519 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374379.pdf [firstpage_image] =>[orig_patent_app_number] => 09245519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245519
Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment Feb 4, 1999 Issued
Array ( [id] => 4325156 [patent_doc_number] => 06327683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Device scan testing' [patent_app_type] => 1 [patent_app_number] => 9/240225 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327683.pdf [firstpage_image] =>[orig_patent_app_number] => 240225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/240225
Device scan testing Jan 28, 1999 Issued
Array ( [id] => 4295279 [patent_doc_number] => 06324664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Means for testing dynamic integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/238112 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2877 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324664.pdf [firstpage_image] =>[orig_patent_app_number] => 238112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238112
Means for testing dynamic integrated circuits Jan 26, 1999 Issued
Array ( [id] => 4291093 [patent_doc_number] => 06308296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Coded image recording device and method' [patent_app_type] => 1 [patent_app_number] => 9/224833 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 8602 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308296.pdf [firstpage_image] =>[orig_patent_app_number] => 224833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224833
Coded image recording device and method Jan 3, 1999 Issued
Array ( [id] => 1592539 [patent_doc_number] => 06360344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information' [patent_app_type] => B1 [patent_app_number] => 09/224137 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5505 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360344.pdf [firstpage_image] =>[orig_patent_app_number] => 09224137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224137
Built in self test algorithm that efficiently detects address related faults of a multiport memory without detailed placement and routing information Dec 30, 1998 Issued
Array ( [id] => 4374675 [patent_doc_number] => 06292911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Error detection scheme for a high-speed data channel' [patent_app_type] => 1 [patent_app_number] => 9/215430 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6372 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292911.pdf [firstpage_image] =>[orig_patent_app_number] => 215430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215430
Error detection scheme for a high-speed data channel Dec 16, 1998 Issued
Array ( [id] => 1602138 [patent_doc_number] => 06385747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Testing of replicated components of electronic device' [patent_app_type] => B1 [patent_app_number] => 09/212314 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385747.pdf [firstpage_image] =>[orig_patent_app_number] => 09212314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212314
Testing of replicated components of electronic device Dec 13, 1998 Issued
Array ( [id] => 1490298 [patent_doc_number] => 06367042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Testing methodology for embedded memories using built-in self repair and identification circuitry' [patent_app_type] => B1 [patent_app_number] => 09/209996 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367042.pdf [firstpage_image] =>[orig_patent_app_number] => 09209996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209996
Testing methodology for embedded memories using built-in self repair and identification circuitry Dec 10, 1998 Issued
Array ( [id] => 4319058 [patent_doc_number] => 06182267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Ensuring accurate data checksum' [patent_app_type] => 1 [patent_app_number] => 9/197225 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182267.pdf [firstpage_image] =>[orig_patent_app_number] => 197225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197225
Ensuring accurate data checksum Nov 19, 1998 Issued
Array ( [id] => 4404739 [patent_doc_number] => 06263465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Error detection and correction in systems receiving NRZ signals from transmission of RZ signals' [patent_app_type] => 1 [patent_app_number] => 9/196984 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263465.pdf [firstpage_image] =>[orig_patent_app_number] => 196984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196984
Error detection and correction in systems receiving NRZ signals from transmission of RZ signals Nov 19, 1998 Issued
Array ( [id] => 1553868 [patent_doc_number] => 06347385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Interleavers for turbo code' [patent_app_type] => B1 [patent_app_number] => 09/196461 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2670 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347385.pdf [firstpage_image] =>[orig_patent_app_number] => 09196461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196461
Interleavers for turbo code Nov 18, 1998 Issued
Array ( [id] => 4326256 [patent_doc_number] => 06253342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/190438 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5850 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253342.pdf [firstpage_image] =>[orig_patent_app_number] => 190438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190438
Semiconductor integrated circuit Nov 12, 1998 Issued
Array ( [id] => 4424990 [patent_doc_number] => 06230289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Testing data packets' [patent_app_type] => 1 [patent_app_number] => 9/179195 [patent_app_country] => US [patent_app_date] => 1998-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5902 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230289.pdf [firstpage_image] =>[orig_patent_app_number] => 179195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179195
Testing data packets Oct 26, 1998 Issued
Array ( [id] => 4366844 [patent_doc_number] => 06286121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/177115 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9937 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286121.pdf [firstpage_image] =>[orig_patent_app_number] => 177115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177115
Semiconductor device Oct 21, 1998 Issued
Array ( [id] => 4392670 [patent_doc_number] => 06289485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for adding and encoding error correcting codes and its device and method for transmitting data having error correcting codes added' [patent_app_type] => 1 [patent_app_number] => 9/177692 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5209 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289485.pdf [firstpage_image] =>[orig_patent_app_number] => 177692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177692
Method for adding and encoding error correcting codes and its device and method for transmitting data having error correcting codes added Oct 21, 1998 Issued
Array ( [id] => 4352558 [patent_doc_number] => 06314539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Boundary-scan register cell with bypass circuit' [patent_app_type] => 1 [patent_app_number] => 9/176659 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314539.pdf [firstpage_image] =>[orig_patent_app_number] => 176659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176659
Boundary-scan register cell with bypass circuit Oct 20, 1998 Issued
Array ( [id] => 4352546 [patent_doc_number] => 06314538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/175518 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2903 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314538.pdf [firstpage_image] =>[orig_patent_app_number] => 175518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175518
Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit Oct 19, 1998 Issued
Array ( [id] => 4382107 [patent_doc_number] => 06256763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Reed-Solomon decoder having a new polynomial arrangement architecture and decoding method therefor' [patent_app_type] => 1 [patent_app_number] => 9/172081 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256763.pdf [firstpage_image] =>[orig_patent_app_number] => 172081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172081
Reed-Solomon decoder having a new polynomial arrangement architecture and decoding method therefor Oct 13, 1998 Issued
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