Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4271194 [patent_doc_number] => 06223320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Efficient CRC generation utilizing parallel table lookup operations' [patent_app_type] => 1 [patent_app_number] => 9/021516 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5795 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223320.pdf [firstpage_image] =>[orig_patent_app_number] => 021516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021516
Efficient CRC generation utilizing parallel table lookup operations Feb 9, 1998 Issued
Array ( [id] => 4149224 [patent_doc_number] => 06016566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Comparator for semiconductor testing device' [patent_app_type] => 1 [patent_app_number] => 8/913349 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2789 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016566.pdf [firstpage_image] =>[orig_patent_app_number] => 913349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/913349
Comparator for semiconductor testing device Feb 8, 1998 Issued
Array ( [id] => 4148424 [patent_doc_number] => 06128764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Quantum error-correcting codes and devices' [patent_app_type] => 1 [patent_app_number] => 9/019149 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8522 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128764.pdf [firstpage_image] =>[orig_patent_app_number] => 019149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019149
Quantum error-correcting codes and devices Feb 5, 1998 Issued
Array ( [id] => 4318917 [patent_doc_number] => 06182258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and apparatus for test generation during circuit design' [patent_app_type] => 1 [patent_app_number] => 9/020792 [patent_app_country] => US [patent_app_date] => 1998-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11612 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182258.pdf [firstpage_image] =>[orig_patent_app_number] => 020792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020792
Method and apparatus for test generation during circuit design Feb 5, 1998 Issued
Array ( [id] => 4260937 [patent_doc_number] => 06092227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Test circuit' [patent_app_type] => 1 [patent_app_number] => 9/018934 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6447 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092227.pdf [firstpage_image] =>[orig_patent_app_number] => 018934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018934
Test circuit Feb 4, 1998 Issued
Array ( [id] => 4124732 [patent_doc_number] => 06101626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for choosing coding schemes, mappings, and puncturing rates for modulations/encoding systems' [patent_app_type] => 1 [patent_app_number] => 9/018678 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2430 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101626.pdf [firstpage_image] =>[orig_patent_app_number] => 018678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018678
Method for choosing coding schemes, mappings, and puncturing rates for modulations/encoding systems Feb 3, 1998 Issued
Array ( [id] => 4237961 [patent_doc_number] => 06112326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Precoding technique to lower the bit error rate (BER) of punctured convolutional codes' [patent_app_type] => 1 [patent_app_number] => 9/017387 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112326.pdf [firstpage_image] =>[orig_patent_app_number] => 017387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017387
Precoding technique to lower the bit error rate (BER) of punctured convolutional codes Feb 1, 1998 Issued
Array ( [id] => 4195854 [patent_doc_number] => 06085351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Synchronization method' [patent_app_type] => 1 [patent_app_number] => 9/011245 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3151 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085351.pdf [firstpage_image] =>[orig_patent_app_number] => 011245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/011245
Synchronization method Jan 29, 1998 Issued
Array ( [id] => 4318902 [patent_doc_number] => 06182257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'BIST memory test system' [patent_app_type] => 1 [patent_app_number] => 9/000968 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4038 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182257.pdf [firstpage_image] =>[orig_patent_app_number] => 000968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000968
BIST memory test system Dec 29, 1997 Issued
Array ( [id] => 4161331 [patent_doc_number] => 06061819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Generation of reproducible random initial states in RTL simulators' [patent_app_type] => 1 [patent_app_number] => 8/999099 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2873 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061819.pdf [firstpage_image] =>[orig_patent_app_number] => 999099 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999099
Generation of reproducible random initial states in RTL simulators Dec 28, 1997 Issued
Array ( [id] => 4195770 [patent_doc_number] => 06085345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Timing control for input/output testability' [patent_app_type] => 1 [patent_app_number] => 8/998487 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5687 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085345.pdf [firstpage_image] =>[orig_patent_app_number] => 998487 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998487
Timing control for input/output testability Dec 23, 1997 Issued
Array ( [id] => 4375201 [patent_doc_number] => 06170075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Data and real-time media communication over a lossy network' [patent_app_type] => 1 [patent_app_number] => 8/993505 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8512 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170075.pdf [firstpage_image] =>[orig_patent_app_number] => 993505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993505
Data and real-time media communication over a lossy network Dec 17, 1997 Issued
Array ( [id] => 4212168 [patent_doc_number] => 06044488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Process for generating a check word for a bit sequence for verifying the integrity and authenticity of the bit sequence' [patent_app_type] => 1 [patent_app_number] => 8/945592 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2019 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044488.pdf [firstpage_image] =>[orig_patent_app_number] => 945592 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/945592
Process for generating a check word for a bit sequence for verifying the integrity and authenticity of the bit sequence Dec 15, 1997 Issued
Array ( [id] => 4212156 [patent_doc_number] => 06044487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Majority voting scheme for hard error sites' [patent_app_type] => 1 [patent_app_number] => 8/991431 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3143 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044487.pdf [firstpage_image] =>[orig_patent_app_number] => 991431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991431
Majority voting scheme for hard error sites Dec 15, 1997 Issued
Array ( [id] => 4121811 [patent_doc_number] => 06023778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method and apparatus for utilizing mux scan flip-flops to test speed related defects by delaying an active to inactive transition of a scan mode signal' [patent_app_type] => 1 [patent_app_number] => 8/989838 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4550 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023778.pdf [firstpage_image] =>[orig_patent_app_number] => 989838 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989838
Method and apparatus for utilizing mux scan flip-flops to test speed related defects by delaying an active to inactive transition of a scan mode signal Dec 11, 1997 Issued
Array ( [id] => 4148379 [patent_doc_number] => 06128761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method and apparatus for G.706 frame alignment and CRC procedure test tool' [patent_app_type] => 1 [patent_app_number] => 8/986830 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5483 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128761.pdf [firstpage_image] =>[orig_patent_app_number] => 986830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986830
Method and apparatus for G.706 frame alignment and CRC procedure test tool Dec 7, 1997 Issued
Array ( [id] => 4157909 [patent_doc_number] => 06061601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Redundant data processing system having two programmed logic controllers operating in tandem' [patent_app_type] => 1 [patent_app_number] => 8/986018 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2753 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061601.pdf [firstpage_image] =>[orig_patent_app_number] => 986018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986018
Redundant data processing system having two programmed logic controllers operating in tandem Dec 4, 1997 Issued
Array ( [id] => 4257778 [patent_doc_number] => 06081921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Bit insertion approach to convolutional encoding' [patent_app_type] => 1 [patent_app_number] => 8/974873 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2940 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081921.pdf [firstpage_image] =>[orig_patent_app_number] => 974873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974873
Bit insertion approach to convolutional encoding Nov 19, 1997 Issued
Array ( [id] => 4100628 [patent_doc_number] => 06055657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Test board for testing IC devices operating in merged data output mode or standard mode' [patent_app_type] => 1 [patent_app_number] => 8/967016 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 4432 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055657.pdf [firstpage_image] =>[orig_patent_app_number] => 967016 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967016
Test board for testing IC devices operating in merged data output mode or standard mode Nov 9, 1997 Issued
Array ( [id] => 4314907 [patent_doc_number] => 06185470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Neural network predictive control method and system' [patent_app_type] => 1 [patent_app_number] => 8/966327 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185470.pdf [firstpage_image] =>[orig_patent_app_number] => 966327 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966327
Neural network predictive control method and system Nov 6, 1997 Issued
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