Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4101636
[patent_doc_number] => 06163870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Message encoding with irregular graphing'
[patent_app_type] => 1
[patent_app_number] => 8/965610
[patent_app_country] => US
[patent_app_date] => 1997-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 14479
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163870.pdf
[firstpage_image] =>[orig_patent_app_number] => 965610
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/965610 | Message encoding with irregular graphing | Nov 5, 1997 | Issued |
Array
(
[id] => 4207229
[patent_doc_number] => 06131180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Trellis coded modulation system'
[patent_app_type] => 1
[patent_app_number] => 8/963482
[patent_app_country] => US
[patent_app_date] => 1997-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4868
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/131/06131180.pdf
[firstpage_image] =>[orig_patent_app_number] => 963482
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963482 | Trellis coded modulation system | Nov 2, 1997 | Issued |
Array
(
[id] => 4156780
[patent_doc_number] => 06122766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Reed-Solomon decoder having a three-stage pipeline structure'
[patent_app_type] => 1
[patent_app_number] => 8/951525
[patent_app_country] => US
[patent_app_date] => 1997-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6192
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122766.pdf
[firstpage_image] =>[orig_patent_app_number] => 951525
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/951525 | Reed-Solomon decoder having a three-stage pipeline structure | Oct 15, 1997 | Issued |
Array
(
[id] => 4163007
[patent_doc_number] => 06032276
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Apparatus and method for reading data from a disk type recording media'
[patent_app_type] => 1
[patent_app_number] => 8/947604
[patent_app_country] => US
[patent_app_date] => 1997-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2001
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/032/06032276.pdf
[firstpage_image] =>[orig_patent_app_number] => 947604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947604 | Apparatus and method for reading data from a disk type recording media | Oct 8, 1997 | Issued |
Array
(
[id] => 4255890
[patent_doc_number] => 06119260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Decoder for executing error correction and error detection in parallel'
[patent_app_type] => 1
[patent_app_number] => 8/939992
[patent_app_country] => US
[patent_app_date] => 1997-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4443
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119260.pdf
[firstpage_image] =>[orig_patent_app_number] => 939992
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/939992 | Decoder for executing error correction and error detection in parallel | Sep 28, 1997 | Issued |
Array
(
[id] => 4115270
[patent_doc_number] => 06049903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Digital data error detection and correction system'
[patent_app_type] => 1
[patent_app_number] => 8/935106
[patent_app_country] => US
[patent_app_date] => 1997-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4815
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049903.pdf
[firstpage_image] =>[orig_patent_app_number] => 935106
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/935106 | Digital data error detection and correction system | Sep 28, 1997 | Issued |
Array
(
[id] => 4207174
[patent_doc_number] => 06131177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'System including a ferroelectric memory'
[patent_app_type] => 1
[patent_app_number] => 8/932957
[patent_app_country] => US
[patent_app_date] => 1997-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 7077
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/131/06131177.pdf
[firstpage_image] =>[orig_patent_app_number] => 932957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932957 | System including a ferroelectric memory | Sep 17, 1997 | Issued |
Array
(
[id] => 4118820
[patent_doc_number] => 06098192
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Cost reduced finite field processor for error correction in computer storage devices'
[patent_app_type] => 1
[patent_app_number] => 8/932121
[patent_app_country] => US
[patent_app_date] => 1997-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7189
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/098/06098192.pdf
[firstpage_image] =>[orig_patent_app_number] => 932121
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932121 | Cost reduced finite field processor for error correction in computer storage devices | Sep 16, 1997 | Issued |
Array
(
[id] => 4115242
[patent_doc_number] => 06049901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Test system for integrated circuits using a single memory for both the parallel and scan modes of testing'
[patent_app_type] => 1
[patent_app_number] => 8/931164
[patent_app_country] => US
[patent_app_date] => 1997-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4382
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049901.pdf
[firstpage_image] =>[orig_patent_app_number] => 931164
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/931164 | Test system for integrated circuits using a single memory for both the parallel and scan modes of testing | Sep 15, 1997 | Issued |
Array
(
[id] => 4281591
[patent_doc_number] => 06260165
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Accelerating scan test by re-using response data as stimulus data'
[patent_app_type] => 1
[patent_app_number] => 8/931791
[patent_app_country] => US
[patent_app_date] => 1997-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 34
[patent_no_of_words] => 13084
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/260/06260165.pdf
[firstpage_image] =>[orig_patent_app_number] => 931791
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/931791 | Accelerating scan test by re-using response data as stimulus data | Sep 15, 1997 | Issued |
Array
(
[id] => 4177474
[patent_doc_number] => 06158038
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method and apparatus for correcting data errors'
[patent_app_type] => 1
[patent_app_number] => 8/929063
[patent_app_country] => US
[patent_app_date] => 1997-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 10102
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/158/06158038.pdf
[firstpage_image] =>[orig_patent_app_number] => 929063
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929063 | Method and apparatus for correcting data errors | Sep 14, 1997 | Issued |
Array
(
[id] => 4015530
[patent_doc_number] => 05925146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Reception data expander having noise reduced in generation of reception data error'
[patent_app_type] => 1
[patent_app_number] => 8/924503
[patent_app_country] => US
[patent_app_date] => 1997-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 44
[patent_no_of_words] => 18333
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/925/05925146.pdf
[firstpage_image] =>[orig_patent_app_number] => 924503
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/924503 | Reception data expander having noise reduced in generation of reception data error | Sep 4, 1997 | Issued |
Array
(
[id] => 4116912
[patent_doc_number] => 06067655
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Burst error limiting symbol detector system'
[patent_app_type] => 1
[patent_app_number] => 8/919868
[patent_app_country] => US
[patent_app_date] => 1997-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3344
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/067/06067655.pdf
[firstpage_image] =>[orig_patent_app_number] => 919868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919868 | Burst error limiting symbol detector system | Aug 27, 1997 | Issued |
Array
(
[id] => 4195825
[patent_doc_number] => 06085349
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Method for selecting cyclic redundancy check polynomials for linear coded systems'
[patent_app_type] => 1
[patent_app_number] => 8/920626
[patent_app_country] => US
[patent_app_date] => 1997-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6607
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/085/06085349.pdf
[firstpage_image] =>[orig_patent_app_number] => 920626
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/920626 | Method for selecting cyclic redundancy check polynomials for linear coded systems | Aug 26, 1997 | Issued |
Array
(
[id] => 4266653
[patent_doc_number] => 06138049
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'System and methods for generating and distributing alarm and event notifications'
[patent_app_type] => 1
[patent_app_number] => 8/916871
[patent_app_country] => US
[patent_app_date] => 1997-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5732
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138049.pdf
[firstpage_image] =>[orig_patent_app_number] => 916871
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/916871 | System and methods for generating and distributing alarm and event notifications | Aug 21, 1997 | Issued |
Array
(
[id] => 4426774
[patent_doc_number] => 06178536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Coding scheme for file backup and systems based thereon'
[patent_app_type] => 1
[patent_app_number] => 8/911126
[patent_app_country] => US
[patent_app_date] => 1997-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6482
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/178/06178536.pdf
[firstpage_image] =>[orig_patent_app_number] => 911126
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911126 | Coding scheme for file backup and systems based thereon | Aug 13, 1997 | Issued |
Array
(
[id] => 4152638
[patent_doc_number] => 06035432
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'System for remapping defective memory bit sets'
[patent_app_type] => 1
[patent_app_number] => 8/903819
[patent_app_country] => US
[patent_app_date] => 1997-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5996
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/035/06035432.pdf
[firstpage_image] =>[orig_patent_app_number] => 903819
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/903819 | System for remapping defective memory bit sets | Jul 30, 1997 | Issued |
Array
(
[id] => 3940234
[patent_doc_number] => 05954837
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Method for optimizing viterbi detector threshold values'
[patent_app_type] => 1
[patent_app_number] => 8/903837
[patent_app_country] => US
[patent_app_date] => 1997-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4584
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/954/05954837.pdf
[firstpage_image] =>[orig_patent_app_number] => 903837
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/903837 | Method for optimizing viterbi detector threshold values | Jul 30, 1997 | Issued |
Array
(
[id] => 4110996
[patent_doc_number] => 06134695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Code image data output apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 8/900959
[patent_app_country] => US
[patent_app_date] => 1997-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 51
[patent_figures_cnt] => 89
[patent_no_of_words] => 29233
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/134/06134695.pdf
[firstpage_image] =>[orig_patent_app_number] => 900959
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900959 | Code image data output apparatus and method | Jul 24, 1997 | Issued |
Array
(
[id] => 3962654
[patent_doc_number] => 05974580
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Concurrent row/column syndrome generator for a product code'
[patent_app_type] => 1
[patent_app_number] => 8/898774
[patent_app_country] => US
[patent_app_date] => 1997-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7346
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/974/05974580.pdf
[firstpage_image] =>[orig_patent_app_number] => 898774
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/898774 | Concurrent row/column syndrome generator for a product code | Jul 22, 1997 | Issued |