Search

Mang Hang Yeung

Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2416, 2463
Total Applications
761
Issued Applications
610
Pending Applications
64
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4124618 [patent_doc_number] => 06101620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory' [patent_app_type] => 1 [patent_app_number] => 8/896970 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8042 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 448 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101620.pdf [firstpage_image] =>[orig_patent_app_number] => 896970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896970
Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory Jul 17, 1997 Issued
Array ( [id] => 4163103 [patent_doc_number] => 06032283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'System for correcting errors in data frames having horizontal and vertical parity codes' [patent_app_type] => 1 [patent_app_number] => 8/893217 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7613 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032283.pdf [firstpage_image] =>[orig_patent_app_number] => 893217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893217
System for correcting errors in data frames having horizontal and vertical parity codes Jul 14, 1997 Issued
Array ( [id] => 4114100 [patent_doc_number] => 06097889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals' [patent_app_type] => 1 [patent_app_number] => 8/880956 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7131 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097889.pdf [firstpage_image] =>[orig_patent_app_number] => 880956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880956
Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals Jun 22, 1997 Issued
Array ( [id] => 3971711 [patent_doc_number] => 06000053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Error correction and loss recovery of packets over a computer network' [patent_app_type] => 1 [patent_app_number] => 8/876139 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2685 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000053.pdf [firstpage_image] =>[orig_patent_app_number] => 876139 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876139
Error correction and loss recovery of packets over a computer network Jun 12, 1997 Issued
Array ( [id] => 3967568 [patent_doc_number] => 05983337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction' [patent_app_type] => 1 [patent_app_number] => 8/873733 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16387 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983337.pdf [firstpage_image] =>[orig_patent_app_number] => 873733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873733
Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction Jun 11, 1997 Issued
Array ( [id] => 4373990 [patent_doc_number] => 06175890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Device for efficiently handling interrupt request processes' [patent_app_type] => 1 [patent_app_number] => 8/873307 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3601 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175890.pdf [firstpage_image] =>[orig_patent_app_number] => 873307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873307
Device for efficiently handling interrupt request processes Jun 10, 1997 Issued
Array ( [id] => 3975330 [patent_doc_number] => 05984504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Safety or protection system employing reflective memory and/or diverse processors and communications' [patent_app_type] => 1 [patent_app_number] => 8/873350 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6600 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/984/05984504.pdf [firstpage_image] =>[orig_patent_app_number] => 873350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873350
Safety or protection system employing reflective memory and/or diverse processors and communications Jun 10, 1997 Issued
Array ( [id] => 4205277 [patent_doc_number] => 06131050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Control device having a control logic switching function' [patent_app_type] => 1 [patent_app_number] => 8/872707 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1390 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131050.pdf [firstpage_image] =>[orig_patent_app_number] => 872707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872707
Control device having a control logic switching function Jun 10, 1997 Issued
Array ( [id] => 3971405 [patent_doc_number] => 05991913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Error correcting device' [patent_app_type] => 1 [patent_app_number] => 8/872155 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 57 [patent_no_of_words] => 14031 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991913.pdf [firstpage_image] =>[orig_patent_app_number] => 872155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872155
Error correcting device Jun 9, 1997 Issued
Array ( [id] => 4267753 [patent_doc_number] => 06223093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'System and method for verifying process procedures in a manufacturing environment' [patent_app_type] => 1 [patent_app_number] => 8/871196 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223093.pdf [firstpage_image] =>[orig_patent_app_number] => 871196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871196
System and method for verifying process procedures in a manufacturing environment Jun 8, 1997 Issued
Array ( [id] => 4422042 [patent_doc_number] => 06240330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for feedforward corrections for off-specification conditions' [patent_app_type] => 1 [patent_app_number] => 8/864303 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1815 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240330.pdf [firstpage_image] =>[orig_patent_app_number] => 864303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864303
Method for feedforward corrections for off-specification conditions May 27, 1997 Issued
Array ( [id] => 3993369 [patent_doc_number] => 05949680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Printed plastic card job control system' [patent_app_type] => 1 [patent_app_number] => 8/864123 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6326 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949680.pdf [firstpage_image] =>[orig_patent_app_number] => 864123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864123
Printed plastic card job control system May 27, 1997 Issued
Array ( [id] => 4195425 [patent_doc_number] => 06085324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Monitoring and regulatory system for the internet' [patent_app_type] => 1 [patent_app_number] => 8/856324 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5777 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085324.pdf [firstpage_image] =>[orig_patent_app_number] => 856324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856324
Monitoring and regulatory system for the internet May 13, 1997 Issued
Array ( [id] => 4178577 [patent_doc_number] => 06108809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for sending messages from a lower-level controller to a higher-level controller' [patent_app_type] => 1 [patent_app_number] => 8/836499 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2650 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108809.pdf [firstpage_image] =>[orig_patent_app_number] => 836499 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/836499
Method for sending messages from a lower-level controller to a higher-level controller May 6, 1997 Issued
Array ( [id] => 4118417 [patent_doc_number] => 06098164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Microprocessor with common bus for memory and peripheral circuit having data latch generator' [patent_app_type] => 1 [patent_app_number] => 8/851075 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3550 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098164.pdf [firstpage_image] =>[orig_patent_app_number] => 851075 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851075
Microprocessor with common bus for memory and peripheral circuit having data latch generator May 4, 1997 Issued
Array ( [id] => 4202899 [patent_doc_number] => 06094740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Channel quality estimator based on non-redundant error correction' [patent_app_type] => 1 [patent_app_number] => 8/846633 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2319 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094740.pdf [firstpage_image] =>[orig_patent_app_number] => 846633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846633
Channel quality estimator based on non-redundant error correction Apr 29, 1997 Issued
Array ( [id] => 4226291 [patent_doc_number] => 06029264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'System and method for error correcting a received data stream in a concatenated system' [patent_app_type] => 1 [patent_app_number] => 8/840383 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 6850 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029264.pdf [firstpage_image] =>[orig_patent_app_number] => 840383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840383
System and method for error correcting a received data stream in a concatenated system Apr 27, 1997 Issued
Array ( [id] => 4006266 [patent_doc_number] => 05920578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and apparatus for efficiently processing a multi-dimensional code' [patent_app_type] => 1 [patent_app_number] => 8/842147 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 13779 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920578.pdf [firstpage_image] =>[orig_patent_app_number] => 842147 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842147
Method and apparatus for efficiently processing a multi-dimensional code Apr 22, 1997 Issued
Array ( [id] => 4023015 [patent_doc_number] => 05987638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Apparatus and method for computing the result of a viterbi equation in a single cycle' [patent_app_type] => 1 [patent_app_number] => 8/841415 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3869 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987638.pdf [firstpage_image] =>[orig_patent_app_number] => 841415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841415
Apparatus and method for computing the result of a viterbi equation in a single cycle Apr 21, 1997 Issued
Array ( [id] => 4064204 [patent_doc_number] => 05964896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method and apparatus for a high speed cyclical redundancy check system' [patent_app_type] => 1 [patent_app_number] => 8/839873 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 3146 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964896.pdf [firstpage_image] =>[orig_patent_app_number] => 839873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839873
Method and apparatus for a high speed cyclical redundancy check system Apr 16, 1997 Issued
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