Mang Hang Yeung
Examiner (ID: 1315, Phone: (571)270-7319 , Office: P/2463 )
Most Active Art Unit | 2463 |
Art Unit(s) | 2416, 2463 |
Total Applications | 761 |
Issued Applications | 610 |
Pending Applications | 64 |
Abandoned Applications | 87 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4124618
[patent_doc_number] => 06101620
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory'
[patent_app_type] => 1
[patent_app_number] => 8/896970
[patent_app_country] => US
[patent_app_date] => 1997-07-18
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[pdf_file] => patents/06/101/06101620.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896970 | Testable interleaved dual-DRAM architecture for a video memory controller with split internal/external memory | Jul 17, 1997 | Issued |
Array
(
[id] => 4163103
[patent_doc_number] => 06032283
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'System for correcting errors in data frames having horizontal and vertical parity codes'
[patent_app_type] => 1
[patent_app_number] => 8/893217
[patent_app_country] => US
[patent_app_date] => 1997-07-15
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[pdf_file] => patents/06/032/06032283.pdf
[firstpage_image] =>[orig_patent_app_number] => 893217
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893217 | System for correcting errors in data frames having horizontal and vertical parity codes | Jul 14, 1997 | Issued |
Array
(
[id] => 4114100
[patent_doc_number] => 06097889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals'
[patent_app_type] => 1
[patent_app_number] => 8/880956
[patent_app_country] => US
[patent_app_date] => 1997-06-23
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[firstpage_image] =>[orig_patent_app_number] => 880956
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880956 | Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals | Jun 22, 1997 | Issued |
Array
(
[id] => 3971711
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Error correction and loss recovery of packets over a computer network'
[patent_app_type] => 1
[patent_app_number] => 8/876139
[patent_app_country] => US
[patent_app_date] => 1997-06-13
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[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/876139 | Error correction and loss recovery of packets over a computer network | Jun 12, 1997 | Issued |
Array
(
[id] => 3967568
[patent_doc_number] => 05983337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction'
[patent_app_type] => 1
[patent_app_number] => 8/873733
[patent_app_country] => US
[patent_app_date] => 1997-06-12
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[pdf_file] => patents/05/983/05983337.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873733 | Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction | Jun 11, 1997 | Issued |
Array
(
[id] => 4373990
[patent_doc_number] => 06175890
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[patent_issue_date] => 2001-01-16
[patent_title] => 'Device for efficiently handling interrupt request processes'
[patent_app_type] => 1
[patent_app_number] => 8/873307
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873307 | Device for efficiently handling interrupt request processes | Jun 10, 1997 | Issued |
Array
(
[id] => 3975330
[patent_doc_number] => 05984504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Safety or protection system employing reflective memory and/or diverse processors and communications'
[patent_app_type] => 1
[patent_app_number] => 8/873350
[patent_app_country] => US
[patent_app_date] => 1997-06-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/984/05984504.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873350 | Safety or protection system employing reflective memory and/or diverse processors and communications | Jun 10, 1997 | Issued |
Array
(
[id] => 4205277
[patent_doc_number] => 06131050
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Control device having a control logic switching function'
[patent_app_type] => 1
[patent_app_number] => 8/872707
[patent_app_country] => US
[patent_app_date] => 1997-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/131/06131050.pdf
[firstpage_image] =>[orig_patent_app_number] => 872707
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/872707 | Control device having a control logic switching function | Jun 10, 1997 | Issued |
Array
(
[id] => 3971405
[patent_doc_number] => 05991913
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Error correcting device'
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[patent_app_number] => 8/872155
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/872155 | Error correcting device | Jun 9, 1997 | Issued |
Array
(
[id] => 4267753
[patent_doc_number] => 06223093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'System and method for verifying process procedures in a manufacturing environment'
[patent_app_type] => 1
[patent_app_number] => 8/871196
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[patent_app_date] => 1997-06-09
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[firstpage_image] =>[orig_patent_app_number] => 871196
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/871196 | System and method for verifying process procedures in a manufacturing environment | Jun 8, 1997 | Issued |
Array
(
[id] => 4422042
[patent_doc_number] => 06240330
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[patent_issue_date] => 2001-05-29
[patent_title] => 'Method for feedforward corrections for off-specification conditions'
[patent_app_type] => 1
[patent_app_number] => 8/864303
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[patent_app_date] => 1997-05-28
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[pdf_file] => patents/06/240/06240330.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/864303 | Method for feedforward corrections for off-specification conditions | May 27, 1997 | Issued |
Array
(
[id] => 3993369
[patent_doc_number] => 05949680
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Printed plastic card job control system'
[patent_app_type] => 1
[patent_app_number] => 8/864123
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[pdf_file] => patents/05/949/05949680.pdf
[firstpage_image] =>[orig_patent_app_number] => 864123
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/864123 | Printed plastic card job control system | May 27, 1997 | Issued |
Array
(
[id] => 4195425
[patent_doc_number] => 06085324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Monitoring and regulatory system for the internet'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/856324 | Monitoring and regulatory system for the internet | May 13, 1997 | Issued |
Array
(
[id] => 4178577
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[patent_issue_date] => 2000-08-22
[patent_title] => 'Method for sending messages from a lower-level controller to a higher-level controller'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/836499 | Method for sending messages from a lower-level controller to a higher-level controller | May 6, 1997 | Issued |
Array
(
[id] => 4118417
[patent_doc_number] => 06098164
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[patent_issue_date] => 2000-08-01
[patent_title] => 'Microprocessor with common bus for memory and peripheral circuit having data latch generator'
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Array
(
[id] => 4202899
[patent_doc_number] => 06094740
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[patent_title] => 'Channel quality estimator based on non-redundant error correction'
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Array
(
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[patent_title] => 'System and method for error correcting a received data stream in a concatenated system'
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Array
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Array
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[patent_title] => 'Apparatus and method for computing the result of a viterbi equation in a single cycle'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/839873 | Method and apparatus for a high speed cyclical redundancy check system | Apr 16, 1997 | Issued |