| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 6814623
[patent_doc_number] => 20030074173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Technique for defining probabilistic reliability test requirements'
[patent_app_type] => new
[patent_app_number] => 09/982061
[patent_app_country] => US
[patent_app_date] => 2001-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4650
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20030074173.pdf
[firstpage_image] =>[orig_patent_app_number] => 09982061
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/982061 | Technique for defining probabilistic reliability test requirements | Oct 16, 2001 | Abandoned |
Array
(
[id] => 7276999
[patent_doc_number] => 20040236450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'Model-based machine diagnostics and prognostics using theory of noise and communications'
[patent_app_type] => new
[patent_app_number] => 09/962633
[patent_app_country] => US
[patent_app_date] => 2001-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 45
[patent_no_of_words] => 18638
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20040236450.pdf
[firstpage_image] =>[orig_patent_app_number] => 09962633
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/962633 | Model-based machine diagnostics and prognostics using theory of noise and communications | Sep 24, 2001 | Abandoned |
Array
(
[id] => 414440
[patent_doc_number] => 07283945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'High level verification of software and hardware descriptions by symbolic simulation using assume-guarantee relationships with linear arithmetic assumptions'
[patent_app_type] => utility
[patent_app_number] => 09/956571
[patent_app_country] => US
[patent_app_date] => 2001-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2865
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/283/07283945.pdf
[firstpage_image] =>[orig_patent_app_number] => 09956571
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/956571 | High level verification of software and hardware descriptions by symbolic simulation using assume-guarantee relationships with linear arithmetic assumptions | Sep 17, 2001 | Issued |
| 09/954715 | Common shared memory in a verification system | Sep 11, 2001 | Abandoned |
Array
(
[id] => 8342584
[patent_doc_number] => 08244512
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-08-14
[patent_title] => 'Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic'
[patent_app_type] => utility
[patent_app_number] => 09/954989
[patent_app_country] => US
[patent_app_date] => 2001-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 112
[patent_figures_cnt] => 126
[patent_no_of_words] => 119465
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 09954989
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/954989 | Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic | Sep 11, 2001 | Issued |
Array
(
[id] => 7365407
[patent_doc_number] => 20040015340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-22
[patent_title] => 'System for forming power system wiring diagram and power supply apparatus and program for use therein'
[patent_app_type] => new
[patent_app_number] => 10/399212
[patent_app_country] => US
[patent_app_date] => 2003-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7719
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20040015340.pdf
[firstpage_image] =>[orig_patent_app_number] => 10399212
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/399212 | Electrical system wiring diagram generating system, and power supply device and program used for the same | Sep 9, 2001 | Issued |
Array
(
[id] => 6751519
[patent_doc_number] => 20030046040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Method and system for architectural space programming for a facility'
[patent_app_type] => new
[patent_app_number] => 09/944747
[patent_app_country] => US
[patent_app_date] => 2001-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3119
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20030046040.pdf
[firstpage_image] =>[orig_patent_app_number] => 09944747
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/944747 | Method and system for architectural space programming for a facility | Aug 30, 2001 | Abandoned |
Array
(
[id] => 929496
[patent_doc_number] => 07315808
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-01
[patent_title] => 'Correlating on-chip data processor trace information for export'
[patent_app_type] => utility
[patent_app_number] => 09/943599
[patent_app_country] => US
[patent_app_date] => 2001-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 30
[patent_no_of_words] => 10920
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/315/07315808.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943599
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943599 | Correlating on-chip data processor trace information for export | Aug 29, 2001 | Issued |
Array
(
[id] => 5829932
[patent_doc_number] => 20020069042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-06
[patent_title] => 'Collecting and exporting on-chip data processor trace and timing information with differing collection and export formats'
[patent_app_type] => new
[patent_app_number] => 09/943595
[patent_app_country] => US
[patent_app_date] => 2001-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10865
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0069/20020069042.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943595 | Collecting and exporting on-chip data processor trace and timing information with differing collection and export formats | Aug 29, 2001 | Issued |
Array
(
[id] => 5875722
[patent_doc_number] => 20020049573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-04-25
[patent_title] => 'Automated system and method for designing model based architectures of information systems'
[patent_app_type] => new
[patent_app_number] => 09/942096
[patent_app_country] => US
[patent_app_date] => 2001-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3976
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20020049573.pdf
[firstpage_image] =>[orig_patent_app_number] => 09942096
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/942096 | Automated system and method for designing model based architectures of information systems | Aug 27, 2001 | Abandoned |
Array
(
[id] => 816062
[patent_doc_number] => 07415401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Method for constructing 3-D geologic models by combining multiple frequency passbands'
[patent_app_type] => utility
[patent_app_number] => 09/934320
[patent_app_country] => US
[patent_app_date] => 2001-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6738
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/415/07415401.pdf
[firstpage_image] =>[orig_patent_app_number] => 09934320
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/934320 | Method for constructing 3-D geologic models by combining multiple frequency passbands | Aug 20, 2001 | Issued |
Array
(
[id] => 6815094
[patent_doc_number] => 20030074644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Marker argumentation for an integrated circuit design tool and file structure'
[patent_app_type] => new
[patent_app_number] => 09/928848
[patent_app_country] => US
[patent_app_date] => 2001-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4817
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20030074644.pdf
[firstpage_image] =>[orig_patent_app_number] => 09928848
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/928848 | Marker argumentation for an integrated circuit design tool and file structure | Aug 12, 2001 | Issued |
Array
(
[id] => 6001202
[patent_doc_number] => 20020029136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-07
[patent_title] => 'Simulator for automatic vehicle transmission controllers'
[patent_app_type] => new
[patent_app_number] => 09/925743
[patent_app_country] => US
[patent_app_date] => 2001-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 10961
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20020029136.pdf
[firstpage_image] =>[orig_patent_app_number] => 09925743
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/925743 | Simulator for automatic vehicle transmission controllers | Aug 9, 2001 | Issued |
Array
(
[id] => 5615345
[patent_doc_number] => 20060117274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Behavior processor system and method'
[patent_app_type] => utility
[patent_app_number] => 09/918600
[patent_app_country] => US
[patent_app_date] => 2001-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 113
[patent_figures_cnt] => 113
[patent_no_of_words] => 119405
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20060117274.pdf
[firstpage_image] =>[orig_patent_app_number] => 09918600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/918600 | Behavior processor system and method | Jul 29, 2001 | Abandoned |
Array
(
[id] => 6309314
[patent_doc_number] => 20020095280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Programmable memory emulator capable of emulating unspecified memory devices'
[patent_app_type] => new
[patent_app_number] => 09/907739
[patent_app_country] => US
[patent_app_date] => 2001-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3615
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20020095280.pdf
[firstpage_image] =>[orig_patent_app_number] => 09907739
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/907739 | Programmable memory emulator capable of emulating unspecified memory devices | Jul 18, 2001 | Abandoned |
Array
(
[id] => 6050078
[patent_doc_number] => 20020169588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Bidirectional wire I/O model and method for device simulation'
[patent_app_type] => new
[patent_app_number] => 09/854038
[patent_app_country] => US
[patent_app_date] => 2001-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4728
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20020169588.pdf
[firstpage_image] =>[orig_patent_app_number] => 09854038
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/854038 | Bidirectional wire I/O model and method for device simulation | May 10, 2001 | Issued |