Search

Marc M. Duncan

Examiner (ID: 7953, Phone: (571)272-3646 , Office: P/2113 )

Most Active Art Unit
2113
Art Unit(s)
2113, 2184
Total Applications
1363
Issued Applications
1163
Pending Applications
82
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16910402 [patent_doc_number] => 11042442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Control plane method and apparatus for providing erasure code protection across multiple storage devices [patent_app_type] => utility [patent_app_number] => 16/289257 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6098 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289257
Control plane method and apparatus for providing erasure code protection across multiple storage devices Feb 27, 2019 Issued
Array ( [id] => 14782315 [patent_doc_number] => 20190266055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => ELECTRONIC DATA-DISTRIBUTION CONTROL UNIT AND METHOD FOR OPERATING SUCH A CONTROL UNIT [patent_app_type] => utility [patent_app_number] => 16/287433 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287433
Electronic data-distribution control unit and method for operating such a control unit Feb 26, 2019 Issued
Array ( [id] => 16804162 [patent_doc_number] => 10999125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Inter-application communication via signal-routes [patent_app_type] => utility [patent_app_number] => 16/278317 [patent_app_country] => US [patent_app_date] => 2019-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 14468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16278317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/278317
Inter-application communication via signal-routes Feb 17, 2019 Issued
Array ( [id] => 14410869 [patent_doc_number] => 20190171278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PROCESSOR DEVICE SUPPLY VOLTAGE CHARACTERIZATION [patent_app_type] => utility [patent_app_number] => 16/259140 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259140
Processor device supply voltage characterization Jan 27, 2019 Issued
Array ( [id] => 17970213 [patent_doc_number] => 11487747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Anomaly location identification device, anomaly location identification method, and program [patent_app_type] => utility [patent_app_number] => 16/961128 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4365 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961128
Anomaly location identification device, anomaly location identification method, and program Dec 25, 2018 Issued
Array ( [id] => 16958361 [patent_doc_number] => 11062233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Methods and apparatus to analyze performance of watermark encoding devices [patent_app_type] => utility [patent_app_number] => 16/231171 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231171
Methods and apparatus to analyze performance of watermark encoding devices Dec 20, 2018 Issued
Array ( [id] => 14506541 [patent_doc_number] => 20190196925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => CONFIGURATION SYSTEM FOR CONFIGURING A TEST SYSTEM SUITABLE FOR TESTING AN ELECTRONIC CONTROL UNIT [patent_app_type] => utility [patent_app_number] => 16/226730 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226730
CONFIGURATION SYSTEM FOR CONFIGURING A TEST SYSTEM SUITABLE FOR TESTING AN ELECTRONIC CONTROL UNIT Dec 19, 2018 Abandoned
Array ( [id] => 17430366 [patent_doc_number] => 20220058075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => IDENTIFYING FAULTS IN SYSTEM DATA [patent_app_type] => utility [patent_app_number] => 17/413426 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413426
IDENTIFYING FAULTS IN SYSTEM DATA Dec 11, 2018 Abandoned
Array ( [id] => 15043001 [patent_doc_number] => 20190332505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/212331 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212331
Memory controller, memory system and operating method thereof Dec 5, 2018 Issued
Array ( [id] => 15967005 [patent_doc_number] => 20200167254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => TECHNIQUES AND SYSTEM FOR OPTIMIZATION DRIVEN BY DYNAMIC RESILIENCE [patent_app_type] => utility [patent_app_number] => 16/202048 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202048
Techniques and system for optimization driven by dynamic resilience Nov 26, 2018 Issued
Array ( [id] => 14250261 [patent_doc_number] => 10275331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-30 [patent_title] => Techniques and system for optimization driven by dynamic resilience [patent_app_type] => utility [patent_app_number] => 16/201660 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201660
Techniques and system for optimization driven by dynamic resilience Nov 26, 2018 Issued
Array ( [id] => 15967005 [patent_doc_number] => 20200167254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => TECHNIQUES AND SYSTEM FOR OPTIMIZATION DRIVEN BY DYNAMIC RESILIENCE [patent_app_type] => utility [patent_app_number] => 16/202048 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202048
Techniques and system for optimization driven by dynamic resilience Nov 26, 2018 Issued
Array ( [id] => 15967005 [patent_doc_number] => 20200167254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => TECHNIQUES AND SYSTEM FOR OPTIMIZATION DRIVEN BY DYNAMIC RESILIENCE [patent_app_type] => utility [patent_app_number] => 16/202048 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202048
Techniques and system for optimization driven by dynamic resilience Nov 26, 2018 Issued
Array ( [id] => 15967005 [patent_doc_number] => 20200167254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => TECHNIQUES AND SYSTEM FOR OPTIMIZATION DRIVEN BY DYNAMIC RESILIENCE [patent_app_type] => utility [patent_app_number] => 16/202048 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202048
Techniques and system for optimization driven by dynamic resilience Nov 26, 2018 Issued
Array ( [id] => 15903045 [patent_doc_number] => 20200151042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => DETERMINING SERVER ERROR TYPES [patent_app_type] => utility [patent_app_number] => 16/189348 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189348
Determining server error types Nov 12, 2018 Issued
Array ( [id] => 14047465 [patent_doc_number] => 20190079839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => LOCALITY BASED QUORUMS [patent_app_type] => utility [patent_app_number] => 16/185423 [patent_app_country] => US [patent_app_date] => 2018-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16185423 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/185423
Locality based quorums Nov 8, 2018 Issued
Array ( [id] => 15870719 [patent_doc_number] => 20200142763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => METRIC-BASED ANOMALY DETECTION SYSTEM WITH EVOLVING MECHANISM IN LARGE-SCALE CLOUD [patent_app_type] => utility [patent_app_number] => 16/181810 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181810
Metric-based anomaly detection system with evolving mechanism in large-scale cloud Nov 5, 2018 Issued
Array ( [id] => 15870731 [patent_doc_number] => 20200142769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => LEVERAGING EXISTING LOGIC PATHS DURING BIT-ACCURATE PROCESSOR TRACING [patent_app_type] => utility [patent_app_number] => 16/180753 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180753
Leveraging existing logic paths during bit-accurate processor tracing Nov 4, 2018 Issued
Array ( [id] => 16574196 [patent_doc_number] => 10896119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Common input/output interface for application and debug circuitry [patent_app_type] => utility [patent_app_number] => 16/180811 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180811
Common input/output interface for application and debug circuitry Nov 4, 2018 Issued
Array ( [id] => 14629051 [patent_doc_number] => 20190227893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => Error Allocation Format Selection for Hardware Implementation of Deep Neural Network [patent_app_type] => utility [patent_app_number] => 16/181104 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181104
Error allocation format selection for hardware implementation of deep neural network Nov 4, 2018 Issued
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