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Marc Winston Butler

Examiner (ID: 15174)

Most Active Art Unit
3726
Art Unit(s)
3206, 3726
Total Applications
359
Issued Applications
297
Pending Applications
23
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19531912 [patent_doc_number] => 20240355814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/760507 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760507
SEMICONDUCTOR DEVICE Jun 30, 2024 Pending
Array ( [id] => 19531912 [patent_doc_number] => 20240355814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/760507 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760507
SEMICONDUCTOR DEVICE Jun 30, 2024 Pending
Array ( [id] => 19517831 [patent_doc_number] => 20240349517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/756056 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756056
SEMICONDUCTOR DEVICE Jun 26, 2024 Pending
Array ( [id] => 19452746 [patent_doc_number] => 20240312876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof [patent_app_type] => utility [patent_app_number] => 18/671580 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671580
Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof May 21, 2024 Pending
Array ( [id] => 19452746 [patent_doc_number] => 20240312876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof [patent_app_type] => utility [patent_app_number] => 18/671580 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671580 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671580
Air Gap Seal for Interconnect Air Gap and Method of Fabricating Thereof May 21, 2024 Pending
Array ( [id] => 19436179 [patent_doc_number] => 20240304677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING AN IGBT WITH REDUCED VARIATION IN THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/665569 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665569
SEMICONDUCTOR DEVICE INCLUDING AN IGBT WITH REDUCED VARIATION IN THRESHOLD VOLTAGE May 15, 2024 Pending
Array ( [id] => 19407271 [patent_doc_number] => 20240290782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/659125 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659125
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE May 8, 2024 Pending
Array ( [id] => 19237338 [patent_doc_number] => 20240194533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING [patent_app_type] => utility [patent_app_number] => 18/389625 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 65228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389625
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING Dec 18, 2023 Pending
Array ( [id] => 19237338 [patent_doc_number] => 20240194533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING [patent_app_type] => utility [patent_app_number] => 18/389625 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 65228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389625
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING Dec 18, 2023 Pending
Array ( [id] => 19086422 [patent_doc_number] => 20240113223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS HAVING INCREASED THRESHOLD VOLTAGE AND RELATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/530113 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530113
SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS HAVING INCREASED THRESHOLD VOLTAGE AND RELATED METHODS AND SYSTEMS Dec 4, 2023 Pending
Array ( [id] => 19038489 [patent_doc_number] => 20240088304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => DIODE INCLUDING A TRENCH ELECTRODE SUBDIVIDED INTO AT LEAST FIRST AND SECOND PARTS [patent_app_type] => utility [patent_app_number] => 18/510906 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510906
DIODE INCLUDING A TRENCH ELECTRODE SUBDIVIDED INTO AT LEAST FIRST AND SECOND PARTS Nov 15, 2023 Pending
Array ( [id] => 18991060 [patent_doc_number] => 20240063029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => PACKAGING STRUCTURE HAVING ORGANIC INTERPOSER LAYER AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/235894 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235894
PACKAGING STRUCTURE HAVING ORGANIC INTERPOSER LAYER AND METHOD FOR MANUFACTURING SAME Aug 20, 2023 Pending
Array ( [id] => 18991060 [patent_doc_number] => 20240063029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => PACKAGING STRUCTURE HAVING ORGANIC INTERPOSER LAYER AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/235894 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235894
PACKAGING STRUCTURE HAVING ORGANIC INTERPOSER LAYER AND METHOD FOR MANUFACTURING SAME Aug 20, 2023 Pending
Array ( [id] => 18812859 [patent_doc_number] => 20230387196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SUPER JUNCTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/448013 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448013
SUPER JUNCTION STRUCTURE Aug 9, 2023 Pending
Array ( [id] => 18898805 [patent_doc_number] => 20240014290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD AND STRUCTURE FOR DIODES WITH BACKSIDE CONTACTS [patent_app_type] => utility [patent_app_number] => 18/446917 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446917
METHOD AND STRUCTURE FOR DIODES WITH BACKSIDE CONTACTS Aug 8, 2023 Pending
Array ( [id] => 18835328 [patent_doc_number] => 20230403855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE VERTICAL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/446827 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446827
Vertical semiconductor device and method for fabricating the vertical semiconductor device Aug 8, 2023 Issued
Array ( [id] => 18835328 [patent_doc_number] => 20230403855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE VERTICAL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/446827 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446827
Vertical semiconductor device and method for fabricating the vertical semiconductor device Aug 8, 2023 Issued
Array ( [id] => 18898805 [patent_doc_number] => 20240014290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD AND STRUCTURE FOR DIODES WITH BACKSIDE CONTACTS [patent_app_type] => utility [patent_app_number] => 18/446917 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446917 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446917
METHOD AND STRUCTURE FOR DIODES WITH BACKSIDE CONTACTS Aug 8, 2023 Pending
Array ( [id] => 18815003 [patent_doc_number] => 20230389341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/362192 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362192
MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME Jul 30, 2023 Pending
Array ( [id] => 18808385 [patent_doc_number] => 20230382718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/359900 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359900
METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Jul 26, 2023 Pending
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