Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11967426 [patent_doc_number] => 20170271579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/604643 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 8599 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604643
MAGNETIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME May 23, 2017 Abandoned
Array ( [id] => 11952396 [patent_doc_number] => 20170256547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/601154 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14909 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601154
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME May 21, 2017 Abandoned
Array ( [id] => 11939864 [patent_doc_number] => 20170244014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'LIGHT EMITTING DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/589544 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5578 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589544 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589544
Light emitting device package May 7, 2017 Issued
Array ( [id] => 11851454 [patent_doc_number] => 20170225946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'INTEGRATION OF LAMINATE MEMS IN BBUL CORELESS PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/493982 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4498 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493982 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493982
INTEGRATION OF LAMINATE MEMS IN BBUL CORELESS PACKAGE Apr 20, 2017 Abandoned
Array ( [id] => 11760385 [patent_doc_number] => 20170207254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'DISPLAY AND ELECTRONIC UNIT' [patent_app_type] => utility [patent_app_number] => 15/478685 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12559 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478685 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478685
DISPLAY AND ELECTRONIC UNIT Apr 3, 2017 Abandoned
Array ( [id] => 16981562 [patent_doc_number] => 20210225799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => BONDING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/087087 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087087
Bonding apparatus including a heater and a cooling flow path used for stacking a plurality of semiconductor chips Mar 23, 2017 Issued
Array ( [id] => 11630873 [patent_doc_number] => 20170141062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 15/419064 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6407 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419064
COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME Jan 29, 2017 Abandoned
Array ( [id] => 11592994 [patent_doc_number] => 20170117406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SEMICONDUCTOR DEVICE WITH ADJACENT SOURCE/DRAIN REGIONS CONNECTED BY A SEMICONDUCTOR BRIDGE, AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/398788 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 19361 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398788
Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same Jan 4, 2017 Issued
Array ( [id] => 11446294 [patent_doc_number] => 20170047315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'Method of Manufacturing a Multi-Chip Semiconductor Power Device' [patent_app_type] => utility [patent_app_number] => 15/338018 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6356 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338018
Method of Manufacturing a Multi-Chip Semiconductor Power Device Oct 27, 2016 Abandoned
Array ( [id] => 11439420 [patent_doc_number] => 20170040440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/296363 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 30720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296363 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/296363
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Oct 17, 2016 Abandoned
Array ( [id] => 11435884 [patent_doc_number] => 20170036905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'MEMS STRUCTURE WITH AN ETCH STOP LAYER BURIED WITHIN INTER-DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 15/295997 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3322 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/295997
MEMS structure with an etch stop layer buried within inter-dielectric layer Oct 16, 2016 Issued
Array ( [id] => 13682745 [patent_doc_number] => 20160380109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => TRANSISTOR HAVING HARD-MASK LAYERS [patent_app_type] => utility [patent_app_number] => 15/263394 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/263394
TRANSISTOR HAVING HARD-MASK LAYERS Sep 12, 2016 Abandoned
Array ( [id] => 13405515 [patent_doc_number] => 20180254300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => PHOTODIODE MATRIX WITH ISOLATED CATHODES [patent_app_type] => utility [patent_app_number] => 15/755516 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755516 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/755516
PHOTODIODE MATRIX WITH ISOLATED CATHODES Aug 25, 2016 Abandoned
Array ( [id] => 16789230 [patent_doc_number] => 10991669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor package using flip-chip technology [patent_app_type] => utility [patent_app_number] => 15/238454 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8781 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238454
Semiconductor package using flip-chip technology Aug 15, 2016 Issued
Array ( [id] => 11315573 [patent_doc_number] => 20160351683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METHOD OF MAKING TRANSISTOR HAVING METAL DIFFUSION BARRIER' [patent_app_type] => utility [patent_app_number] => 15/233515 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233515
Method of making transistor having metal diffusion barrier Aug 9, 2016 Issued
Array ( [id] => 12437055 [patent_doc_number] => 09978869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode [patent_app_type] => utility [patent_app_number] => 15/232519 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10457 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232519
P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode Aug 8, 2016 Issued
Array ( [id] => 12457698 [patent_doc_number] => 09985105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Method of manufacturing a PMOS transistor comprising a dual work function metal gate [patent_app_type] => utility [patent_app_number] => 15/199413 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2428 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199413
Method of manufacturing a PMOS transistor comprising a dual work function metal gate Jun 29, 2016 Issued
Array ( [id] => 11110891 [patent_doc_number] => 20160307861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/194658 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4909 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194658 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194658
Semiconductor package and method for fabricating base for semiconductor package Jun 27, 2016 Issued
Array ( [id] => 11353721 [patent_doc_number] => 20160372462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'CIRCUIT INCORPORATING MULTIPLE GATE STACK COMPOSITIONS' [patent_app_type] => utility [patent_app_number] => 15/192706 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192706
Circuit incorporating multiple gate stack compositions Jun 23, 2016 Issued
Array ( [id] => 15823015 [patent_doc_number] => 10636703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor device for preventing crack in pad region and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 15/152879 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15152879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/152879
Semiconductor device for preventing crack in pad region and fabricating method thereof May 11, 2016 Issued
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