Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10464037 [patent_doc_number] => 20150349052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS' [patent_app_type] => utility [patent_app_number] => 14/824813 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5280 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/824813
Semiconductor structure with varying doping profile and related ICS and devices Aug 11, 2015 Issued
Array ( [id] => 10455568 [patent_doc_number] => 20150340584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'SUSPENDED SUPERCONDUCTING QUBITS' [patent_app_type] => utility [patent_app_number] => 14/812446 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2769 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812446
Suspended superconducting qubits Jul 28, 2015 Issued
Array ( [id] => 12195628 [patent_doc_number] => 09899364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two' [patent_app_type] => utility [patent_app_number] => 14/807447 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2485 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807447 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/807447
Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two Jul 22, 2015 Issued
Array ( [id] => 10426181 [patent_doc_number] => 20150311192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Apparatus for ESD Protection' [patent_app_type] => utility [patent_app_number] => 14/796834 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796834
Fin ESD protection diode and fabrication method thereof Jul 9, 2015 Issued
Array ( [id] => 10426385 [patent_doc_number] => 20150311396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'LIGHT EMITTING DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/794563 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794563
LIGHT EMITTING DEVICE PACKAGE Jul 7, 2015 Abandoned
Array ( [id] => 10418166 [patent_doc_number] => 20150303176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE' [patent_app_type] => utility [patent_app_number] => 14/743124 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743124 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743124
MULTI-CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE Jun 17, 2015 Abandoned
Array ( [id] => 10377818 [patent_doc_number] => 20150262825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHODS OF FABRICATING MULTIPLE GATE STACK COMPOSITIONS' [patent_app_type] => utility [patent_app_number] => 14/726350 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726350
Methods of fabricating multiple gate stack compositions May 28, 2015 Issued
Array ( [id] => 10440685 [patent_doc_number] => 20150325697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'LDMOS WITH IMPROVED BREAKDOWN VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/713819 [patent_app_country] => US [patent_app_date] => 2015-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14713819 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/713819
LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode May 14, 2015 Issued
Array ( [id] => 15200223 [patent_doc_number] => 10497613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Microelectronic conductive routes and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/560245 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4178 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15560245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/560245
Microelectronic conductive routes and methods of making the same Apr 28, 2015 Issued
Array ( [id] => 10455345 [patent_doc_number] => 20150340360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'LATERAL TRANSISTORS AND METHODS WITH LOW-VOLTAGE-DROP SHUNT TO BODY DIODE' [patent_app_type] => utility [patent_app_number] => 14/694929 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5295 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694929 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694929
Lateral transistors and methods with low-voltage-drop shunt to body diode Apr 22, 2015 Issued
Array ( [id] => 10336629 [patent_doc_number] => 20150221634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION' [patent_app_type] => utility [patent_app_number] => 14/685588 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14685588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/685588
Semiconductor device for electrostatic discharge protection Apr 12, 2015 Issued
Array ( [id] => 10281329 [patent_doc_number] => 20150166327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'MICRO-ELECTROMECHANICAL SEMICONDUCTOR COMPONENT' [patent_app_type] => utility [patent_app_number] => 14/631064 [patent_app_country] => US [patent_app_date] => 2015-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 11655 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14631064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/631064
Micro-electromechanical semiconductor component Feb 24, 2015 Issued
Array ( [id] => 10273720 [patent_doc_number] => 20150158717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR COMPONENT' [patent_app_type] => utility [patent_app_number] => 14/622075 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 13318 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622075
Semiconductor component Feb 12, 2015 Issued
Array ( [id] => 14804201 [patent_doc_number] => 10405118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Semiconductor devices having a membrane layer with smooth stress-relieving corrugations and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 14/611953 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 49 [patent_no_of_words] => 6266 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/611953
Semiconductor devices having a membrane layer with smooth stress-relieving corrugations and methods of fabrication thereof Feb 1, 2015 Issued
Array ( [id] => 10247908 [patent_doc_number] => 20150132904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Semiconductor Device and a Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 14/602323 [patent_app_country] => US [patent_app_date] => 2015-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10599 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602323
Semiconductor device and a method of manufacturing the same Jan 21, 2015 Issued
Array ( [id] => 10247944 [patent_doc_number] => 20150132940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'COPPER-CONTAINING C4 BALL-LIMITING METALLURGY STACK FOR ENHANCED RELIABILITY OF PACKAGED STRUCTURES AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 14/596851 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6411 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/596851
Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same Jan 13, 2015 Issued
Array ( [id] => 10652194 [patent_doc_number] => 09368459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Semiconductor chip with seal ring and sacrificial corner pattern' [patent_app_type] => utility [patent_app_number] => 14/581452 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6178 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/581452
Semiconductor chip with seal ring and sacrificial corner pattern Dec 22, 2014 Issued
Array ( [id] => 11415139 [patent_doc_number] => 09561954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Method of fabricating MEMS devices having a plurality of cavities' [patent_app_type] => utility [patent_app_number] => 14/577628 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577628
Method of fabricating MEMS devices having a plurality of cavities Dec 18, 2014 Issued
Array ( [id] => 9905671 [patent_doc_number] => 20150060871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'THIN FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/534217 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19885 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14534217 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/534217
THIN FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME Nov 5, 2014 Abandoned
Array ( [id] => 9895565 [patent_doc_number] => 20150050764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'Method for manufacturing diode' [patent_app_type] => utility [patent_app_number] => 14/530825 [patent_app_country] => US [patent_app_date] => 2014-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4785 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/530825
Double-side organic light emitting diode with composite anode and cathode including transparent metal layers Nov 1, 2014 Issued
Menu