Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9608916 [patent_doc_number] => 08786087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate' [patent_app_type] => utility [patent_app_number] => 12/829633 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3257 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12829633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829633
Semiconductor device having damascene interconnection structure that prevents void formation between interconnections having transparent dielectric substrate Jul 1, 2010 Issued
Array ( [id] => 10844968 [patent_doc_number] => 08872146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Phase-change random access memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/821414 [patent_app_country] => US [patent_app_date] => 2010-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5166 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12821414 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/821414
Phase-change random access memory device and method of manufacturing the same Jun 22, 2010 Issued
Array ( [id] => 8560123 [patent_doc_number] => 08334186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Method of forming a memory device incorporating a resistance variable chalcogenide element' [patent_app_type] => utility [patent_app_number] => 12/819876 [patent_app_country] => US [patent_app_date] => 2010-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5530 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12819876 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/819876
Method of forming a memory device incorporating a resistance variable chalcogenide element Jun 20, 2010 Issued
Array ( [id] => 6494430 [patent_doc_number] => 20100200917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/767681 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8244 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200917.pdf [firstpage_image] =>[orig_patent_app_number] => 12767681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767681
Tri-gate transistor device with stress incorporation layer and method of fabrication Apr 25, 2010 Issued
Array ( [id] => 6393376 [patent_doc_number] => 20100164088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF AND IC CHIP' [patent_app_type] => utility [patent_app_number] => 12/722072 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164088.pdf [firstpage_image] =>[orig_patent_app_number] => 12722072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722072
SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF AND IC CHIP Mar 10, 2010 Abandoned
Array ( [id] => 6293224 [patent_doc_number] => 20100159693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Method of Forming Via Recess in Underlying Conductive Line' [patent_app_type] => utility [patent_app_number] => 12/715175 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159693.pdf [firstpage_image] =>[orig_patent_app_number] => 12715175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715175
Method of Forming Via Recess in Underlying Conductive Line Feb 28, 2010 Abandoned
Array ( [id] => 10092846 [patent_doc_number] => 09129673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Superlattice recording layer for a phase change memory' [patent_app_type] => utility [patent_app_number] => 13/138545 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5923 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13138545 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/138545
Superlattice recording layer for a phase change memory Feb 23, 2010 Issued
Array ( [id] => 8592509 [patent_doc_number] => 08350386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => utility [patent_app_number] => 12/691597 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 46 [patent_no_of_words] => 8067 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12691597 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691597
Top layers of metal for high performance IC's Jan 20, 2010 Issued
Array ( [id] => 6342321 [patent_doc_number] => 20100084686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'ASSYMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS)' [patent_app_type] => utility [patent_app_number] => 12/633371 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5871 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20100084686.pdf [firstpage_image] =>[orig_patent_app_number] => 12633371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/633371
ASSYMETRIC HETERO-DOPED HIGH-VOLTAGE MOSFET (AH2MOS) Dec 7, 2009 Abandoned
Array ( [id] => 11524525 [patent_doc_number] => 09607936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Copper bump joint structures with improved crack resistance' [patent_app_type] => utility [patent_app_number] => 12/619468 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12619468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619468
Copper bump joint structures with improved crack resistance Nov 15, 2009 Issued
Array ( [id] => 12102135 [patent_doc_number] => 09859235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Underbump metallization structure' [patent_app_type] => utility [patent_app_number] => 12/619503 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12619503 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619503
Underbump metallization structure Nov 15, 2009 Issued
Array ( [id] => 11524525 [patent_doc_number] => 09607936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Copper bump joint structures with improved crack resistance' [patent_app_type] => utility [patent_app_number] => 12/619468 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2680 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12619468 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619468
Copper bump joint structures with improved crack resistance Nov 15, 2009 Issued
Array ( [id] => 6517602 [patent_doc_number] => 20100230680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'LIQUID CRYSTAL DISPLAY DEVICE INCLUDING COMMON ELECTRODE AND REFERENCE ELECTRODE' [patent_app_type] => utility [patent_app_number] => 12/618491 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8238 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230680.pdf [firstpage_image] =>[orig_patent_app_number] => 12618491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618491
LIQUID CRYSTAL DISPLAY DEVICE INCLUDING COMMON ELECTRODE AND REFERENCE ELECTRODE Nov 12, 2009 Abandoned
Array ( [id] => 8082849 [patent_doc_number] => 08148743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/603588 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 60 [patent_no_of_words] => 14246 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/148/08148743.pdf [firstpage_image] =>[orig_patent_app_number] => 12603588 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603588
Semiconductor device including semiconductor circuit made from semiconductor element and manufacturing method thereof Oct 21, 2009 Issued
Array ( [id] => 9140770 [patent_doc_number] => 08581233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Variable capacitor single-electron transistor including a P-N junction gate electrode' [patent_app_type] => utility [patent_app_number] => 12/575364 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12575364 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575364
Variable capacitor single-electron transistor including a P-N junction gate electrode Oct 6, 2009 Issued
Array ( [id] => 6058718 [patent_doc_number] => 20110198578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'SILOLES SUBSTITUTED BY FUSED RING SYSTEMS AND USE THEREOF IN ORGANIC ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 13/123173 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 19434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20110198578.pdf [firstpage_image] =>[orig_patent_app_number] => 13123173 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/123173
Siloles substituted by fused ring systems and use thereof in organic electronics Oct 6, 2009 Issued
Array ( [id] => 6336983 [patent_doc_number] => 20100019398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'STRUCTURED SEMICONDUCTOR ELEMENT FOR REDUCING CHARGING EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/575275 [patent_app_country] => US [patent_app_date] => 2009-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3014 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019398.pdf [firstpage_image] =>[orig_patent_app_number] => 12575275 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575275
STRUCTURED SEMICONDUCTOR ELEMENT FOR REDUCING CHARGING EFFECTS Oct 6, 2009 Abandoned
Array ( [id] => 6502310 [patent_doc_number] => 20100013012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'INTEGRATED COMPLEMENTARY LOW VOLTAGE RF-LDMOS' [patent_app_type] => utility [patent_app_number] => 12/553464 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4109 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20100013012.pdf [firstpage_image] =>[orig_patent_app_number] => 12553464 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553464
Integrated complementary low voltage RF-LDMOS Sep 2, 2009 Issued
Array ( [id] => 6632226 [patent_doc_number] => 20100035392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/549308 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8399 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20100035392.pdf [firstpage_image] =>[orig_patent_app_number] => 12549308 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549308
SEMICONDUCTOR DEVICE Aug 26, 2009 Abandoned
Array ( [id] => 8245260 [patent_doc_number] => 08203189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Semiconductor device including gate electrode having a laminate structure and plug electrically connected thereto' [patent_app_type] => utility [patent_app_number] => 12/549298 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 8466 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/203/08203189.pdf [firstpage_image] =>[orig_patent_app_number] => 12549298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549298
Semiconductor device including gate electrode having a laminate structure and plug electrically connected thereto Aug 26, 2009 Issued
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