Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5395042 [patent_doc_number] => 20090315105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'High-voltage vertical transistor structure' [patent_app_type] => utility [patent_app_number] => 12/583745 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5375 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315105.pdf [firstpage_image] =>[orig_patent_app_number] => 12583745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583745
Gate pullback at ends of high-voltage vertical transistor structure Aug 24, 2009 Issued
Array ( [id] => 5303578 [patent_doc_number] => 20090298230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Stacked Module Systems and Methods' [patent_app_type] => utility [patent_app_number] => 12/538720 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3723 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20090298230.pdf [firstpage_image] =>[orig_patent_app_number] => 12538720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538720
Stacked Module Systems and Methods Aug 9, 2009 Abandoned
Array ( [id] => 6169776 [patent_doc_number] => 20110175111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/121893 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8442 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175111.pdf [firstpage_image] =>[orig_patent_app_number] => 13121893 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/121893
SILICON CARBIDE SEMICONDUCTOR DEVICE Aug 6, 2009 Abandoned
Array ( [id] => 4570460 [patent_doc_number] => 07847355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Semiconductor device including transistors with silicided impurity regions' [patent_app_type] => utility [patent_app_number] => 12/534382 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 70 [patent_no_of_words] => 8519 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847355.pdf [firstpage_image] =>[orig_patent_app_number] => 12534382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534382
Semiconductor device including transistors with silicided impurity regions Aug 2, 2009 Issued
Array ( [id] => 5493377 [patent_doc_number] => 20090261405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Non-Volatile Memory Devices' [patent_app_type] => utility [patent_app_number] => 12/491529 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5479 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20090261405.pdf [firstpage_image] =>[orig_patent_app_number] => 12491529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491529
Non-volatile memory devices including first and second blocking layer patterns Jun 24, 2009 Issued
Array ( [id] => 5996445 [patent_doc_number] => 20110114914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'FIELD EFFECT TRANSISTOR AND CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/055807 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10771 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20110114914.pdf [firstpage_image] =>[orig_patent_app_number] => 13055807 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/055807
FIELD EFFECT TRANSISTOR AND CIRCUIT DEVICE Jun 18, 2009 Abandoned
Array ( [id] => 5567435 [patent_doc_number] => 20090250813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/484099 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4211 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20090250813.pdf [firstpage_image] =>[orig_patent_app_number] => 12484099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484099
Integrated circuit system having different-size solder bumps and different-size bonding pads Jun 11, 2009 Issued
Array ( [id] => 5401290 [patent_doc_number] => 20090236603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'PROCESS FOR FORMING A WIRING FILM, A TRANSISTOR, AND AN ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/480150 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7286 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20090236603.pdf [firstpage_image] =>[orig_patent_app_number] => 12480150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480150
PROCESS FOR FORMING A WIRING FILM, A TRANSISTOR, AND AN ELECTRONIC DEVICE Jun 7, 2009 Abandoned
Array ( [id] => 5483258 [patent_doc_number] => 20090273023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'Segmented pillar layout for a high-voltage vertical transistor' [patent_app_type] => utility [patent_app_number] => 12/455462 [patent_app_country] => US [patent_app_date] => 2009-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3037 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273023.pdf [firstpage_image] =>[orig_patent_app_number] => 12455462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/455462
Segmented pillar layout for a high-voltage vertical transistor Jun 1, 2009 Issued
Array ( [id] => 6067668 [patent_doc_number] => 20110042706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'AlxGa(1-x)As Substrate, Epitaxial Wafer for Infrared LEDs, Infrared LED, Method of Manufacturing AlxGa(1-x)As Substrate, Method of Manufacturing Epitaxial Wafer for Infrared LEDs, and Method of Manufacturing Infrared LEDs' [patent_app_type] => utility [patent_app_number] => 12/990646 [patent_app_country] => US [patent_app_date] => 2009-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 25722 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20110042706.pdf [firstpage_image] =>[orig_patent_app_number] => 12990646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/990646
AlxGa(1-x)As Substrate, Epitaxial Wafer for Infrared LEDs, Infrared LED, Method of Manufacturing AlxGa(1-x)As Substrate, Method of Manufacturing Epitaxial Wafer for Infrared LEDs, and Method of Manufacturing Infrared LEDs May 26, 2009 Abandoned
Array ( [id] => 5401351 [patent_doc_number] => 20090236664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/471600 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20090236664.pdf [firstpage_image] =>[orig_patent_app_number] => 12471600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471600
INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING May 25, 2009 Abandoned
Array ( [id] => 5383042 [patent_doc_number] => 20090224286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/469980 [patent_app_country] => US [patent_app_date] => 2009-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4179 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20090224286.pdf [firstpage_image] =>[orig_patent_app_number] => 12469980 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/469980
MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS May 20, 2009 Abandoned
Array ( [id] => 5469940 [patent_doc_number] => 20090243106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION' [patent_app_type] => utility [patent_app_number] => 12/467889 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8435 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243106.pdf [firstpage_image] =>[orig_patent_app_number] => 12467889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467889
STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION May 17, 2009 Abandoned
Array ( [id] => 12554184 [patent_doc_number] => 10014286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Stackable electronics package and method of fabricating same [patent_app_type] => utility [patent_app_number] => 12/463090 [patent_app_country] => US [patent_app_date] => 2009-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5208 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12463090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/463090
Stackable electronics package and method of fabricating same May 7, 2009 Issued
Array ( [id] => 5483304 [patent_doc_number] => 20090273069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/437340 [patent_app_country] => US [patent_app_date] => 2009-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7283 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273069.pdf [firstpage_image] =>[orig_patent_app_number] => 12437340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/437340
LOW PROFILE CHIP SCALE STACKING SYSTEM AND METHOD May 6, 2009 Abandoned
Array ( [id] => 5536825 [patent_doc_number] => 20090218630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING MOS FIELD EFFECT TRANSISTOR HAVING OFFSET SPACERS OR GATE SIDEWALL FILMS ON EITHER SIDE OF GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/434200 [patent_app_country] => US [patent_app_date] => 2009-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4712 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20090218630.pdf [firstpage_image] =>[orig_patent_app_number] => 12434200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434200
SEMICONDUCTOR DEVICE INCLUDING MOS FIELD EFFECT TRANSISTOR HAVING OFFSET SPACERS OR GATE SIDEWALL FILMS ON EITHER SIDE OF GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME Apr 30, 2009 Abandoned
Array ( [id] => 32486 [patent_doc_number] => 07790554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs' [patent_app_type] => utility [patent_app_number] => 12/432393 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 48 [patent_no_of_words] => 11051 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790554.pdf [firstpage_image] =>[orig_patent_app_number] => 12432393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432393
Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs Apr 28, 2009 Issued
Array ( [id] => 4639924 [patent_doc_number] => 08017951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Semiconductor device including a conductive film having a tapered shape' [patent_app_type] => utility [patent_app_number] => 12/424807 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 53 [patent_no_of_words] => 20217 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017951.pdf [firstpage_image] =>[orig_patent_app_number] => 12424807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424807
Semiconductor device including a conductive film having a tapered shape Apr 15, 2009 Issued
Array ( [id] => 7545817 [patent_doc_number] => 08053791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Structure of AC light-emitting diode dies' [patent_app_type] => utility [patent_app_number] => 12/424109 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 3347 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053791.pdf [firstpage_image] =>[orig_patent_app_number] => 12424109 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424109
Structure of AC light-emitting diode dies Apr 14, 2009 Issued
Array ( [id] => 5401354 [patent_doc_number] => 20090236667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING ISOLATION TRENCHES INDUCING DIFFERENT TYPES OF STRAIN' [patent_app_type] => utility [patent_app_number] => 12/419500 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20090236667.pdf [firstpage_image] =>[orig_patent_app_number] => 12419500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/419500
Semiconductor device comprising isolation trenches inducing different types of strain Apr 6, 2009 Issued
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