
Marcos D. Pizarro Crespo
Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 1073 |
| Issued Applications | 704 |
| Pending Applications | 106 |
| Abandoned Applications | 293 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8104837
[patent_doc_number] => 08154065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'Semiconductor memory devices including a vertical channel transistor having a buried bit line'
[patent_app_type] => utility
[patent_app_number] => 12/418879
[patent_app_country] => US
[patent_app_date] => 2009-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 66
[patent_no_of_words] => 8185
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/154/08154065.pdf
[firstpage_image] =>[orig_patent_app_number] => 12418879
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/418879 | Semiconductor memory devices including a vertical channel transistor having a buried bit line | Apr 5, 2009 | Issued |
Array
(
[id] => 5377406
[patent_doc_number] => 20090189245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-30
[patent_title] => 'SEMICONDUCTOR DEVICE WITH SEAL RING'
[patent_app_type] => utility
[patent_app_number] => 12/410170
[patent_app_country] => US
[patent_app_date] => 2009-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6123
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20090189245.pdf
[firstpage_image] =>[orig_patent_app_number] => 12410170
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/410170 | Semiconductor chip with seal ring and sacrificial corner pattern | Mar 23, 2009 | Issued |
Array
(
[id] => 5342830
[patent_doc_number] => 20090181480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'LED heat-radiating substrate and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 12/406978
[patent_app_country] => US
[patent_app_date] => 2009-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1845
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20090181480.pdf
[firstpage_image] =>[orig_patent_app_number] => 12406978
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/406978 | LED heat-radiating substrate and method for making the same | Mar 18, 2009 | Abandoned |
Array
(
[id] => 8006825
[patent_doc_number] => 08084816
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Semiconductor module'
[patent_app_type] => utility
[patent_app_number] => 12/403000
[patent_app_country] => US
[patent_app_date] => 2009-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 38
[patent_no_of_words] => 4907
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084816.pdf
[firstpage_image] =>[orig_patent_app_number] => 12403000
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/403000 | Semiconductor module | Mar 11, 2009 | Issued |
Array
(
[id] => 5580992
[patent_doc_number] => 20090176338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-09
[patent_title] => 'FULLY-DEPLETED (FD)(SOI) MOSFET ACCESS TRANSISTOR AND METHOD OF FABRICATION'
[patent_app_type] => utility
[patent_app_number] => 12/401555
[patent_app_country] => US
[patent_app_date] => 2009-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8583
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20090176338.pdf
[firstpage_image] =>[orig_patent_app_number] => 12401555
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/401555 | Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication | Mar 9, 2009 | Issued |
Array
(
[id] => 5578716
[patent_doc_number] => 20090174062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-09
[patent_title] => 'CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF CIRCUIT BOARD'
[patent_app_type] => utility
[patent_app_number] => 12/401510
[patent_app_country] => US
[patent_app_date] => 2009-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 7953
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20090174062.pdf
[firstpage_image] =>[orig_patent_app_number] => 12401510
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/401510 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF CIRCUIT BOARD | Mar 9, 2009 | Abandoned |
Array
(
[id] => 5495927
[patent_doc_number] => 20090263955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'GaN single crystal substrate and method of making the same'
[patent_app_type] => utility
[patent_app_number] => 12/382180
[patent_app_country] => US
[patent_app_date] => 2009-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 19386
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0263/20090263955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12382180
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/382180 | GaN single crystal substrate and method of making the same | Mar 9, 2009 | Abandoned |
Array
(
[id] => 7504945
[patent_doc_number] => 08035237
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-11
[patent_title] => 'Integrated circuit package system with heat slug'
[patent_app_type] => utility
[patent_app_number] => 12/398163
[patent_app_country] => US
[patent_app_date] => 2009-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 3001
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/035/08035237.pdf
[firstpage_image] =>[orig_patent_app_number] => 12398163
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/398163 | Integrated circuit package system with heat slug | Mar 3, 2009 | Issued |
Array
(
[id] => 23285
[patent_doc_number] => 07800164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Nanocrystal non-volatile memory cell and method therefor'
[patent_app_type] => utility
[patent_app_number] => 12/397849
[patent_app_country] => US
[patent_app_date] => 2009-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2571
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800164.pdf
[firstpage_image] =>[orig_patent_app_number] => 12397849
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/397849 | Nanocrystal non-volatile memory cell and method therefor | Mar 3, 2009 | Issued |
Array
(
[id] => 5499319
[patent_doc_number] => 20090160007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'Systems and Methods for biasing high fill-factor sensor arrays and the like'
[patent_app_type] => utility
[patent_app_number] => 12/392943
[patent_app_country] => US
[patent_app_date] => 2009-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4662
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20090160007.pdf
[firstpage_image] =>[orig_patent_app_number] => 12392943
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/392943 | Systems and methods for biasing high fill-factor sensor arrays and the like | Feb 24, 2009 | Issued |
Array
(
[id] => 4445945
[patent_doc_number] => 07863703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-04
[patent_title] => 'Systems and methods for biasing high fill-factor sensor arrays and the like'
[patent_app_type] => utility
[patent_app_number] => 12/379581
[patent_app_country] => US
[patent_app_date] => 2009-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4662
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/863/07863703.pdf
[firstpage_image] =>[orig_patent_app_number] => 12379581
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/379581 | Systems and methods for biasing high fill-factor sensor arrays and the like | Feb 24, 2009 | Issued |
Array
(
[id] => 5536812
[patent_doc_number] => 20090218617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-03
[patent_title] => 'SUPERJUNCTION POWER SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/372639
[patent_app_country] => US
[patent_app_date] => 2009-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1517
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20090218617.pdf
[firstpage_image] =>[orig_patent_app_number] => 12372639
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/372639 | SUPERJUNCTION POWER SEMICONDUCTOR DEVICE | Feb 16, 2009 | Abandoned |
Array
(
[id] => 4462455
[patent_doc_number] => 07880304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Post passivation interconnection schemes on top of the IC chips'
[patent_app_type] => utility
[patent_app_number] => 12/370617
[patent_app_country] => US
[patent_app_date] => 2009-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 26
[patent_no_of_words] => 11529
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/880/07880304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12370617
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/370617 | Post passivation interconnection schemes on top of the IC chips | Feb 12, 2009 | Issued |
Array
(
[id] => 5353050
[patent_doc_number] => 20090184394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'High performance system-on-chip inductor using post passivation process'
[patent_app_type] => utility
[patent_app_number] => 12/365180
[patent_app_country] => US
[patent_app_date] => 2009-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 8791
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20090184394.pdf
[firstpage_image] =>[orig_patent_app_number] => 12365180
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/365180 | High performance system-on-chip inductor using post passivation process | Feb 3, 2009 | Abandoned |
Array
(
[id] => 7595188
[patent_doc_number] => 07626273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-01
[patent_title] => 'Low profile stacking system and method'
[patent_app_type] => utility
[patent_app_number] => 12/356432
[patent_app_country] => US
[patent_app_date] => 2009-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3330
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/626/07626273.pdf
[firstpage_image] =>[orig_patent_app_number] => 12356432
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/356432 | Low profile stacking system and method | Jan 19, 2009 | Issued |
Array
(
[id] => 5561605
[patent_doc_number] => 20090134457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'Segmented pillar layout for a high-voltage vertical transistor'
[patent_app_type] => utility
[patent_app_number] => 12/321250
[patent_app_country] => US
[patent_app_date] => 2009-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2991
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20090134457.pdf
[firstpage_image] =>[orig_patent_app_number] => 12321250
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/321250 | Segmented pillar layout for a high-voltage vertical transistor | Jan 19, 2009 | Issued |
Array
(
[id] => 5340652
[patent_doc_number] => 20090179302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'PROGRAMMABLE ELECTRONIC FUSE'
[patent_app_type] => utility
[patent_app_number] => 12/355056
[patent_app_country] => US
[patent_app_date] => 2009-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4439
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20090179302.pdf
[firstpage_image] =>[orig_patent_app_number] => 12355056
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/355056 | PROGRAMMABLE ELECTRONIC FUSE | Jan 15, 2009 | Abandoned |
Array
(
[id] => 5407440
[patent_doc_number] => 20090121338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'ASSEMBLIES AND MULTI CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE HAVING CENTRALLY LOCATED, WIRE BONDED BOND PADS'
[patent_app_type] => utility
[patent_app_number] => 12/354059
[patent_app_country] => US
[patent_app_date] => 2009-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9168
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20090121338.pdf
[firstpage_image] =>[orig_patent_app_number] => 12354059
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/354059 | Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded bond pads | Jan 14, 2009 | Issued |
Array
(
[id] => 4564546
[patent_doc_number] => 07838990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'High-frequency hermetically-sealed circuit package'
[patent_app_type] => utility
[patent_app_number] => 12/353100
[patent_app_country] => US
[patent_app_date] => 2009-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3305
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/838/07838990.pdf
[firstpage_image] =>[orig_patent_app_number] => 12353100
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/353100 | High-frequency hermetically-sealed circuit package | Jan 12, 2009 | Issued |
Array
(
[id] => 5419759
[patent_doc_number] => 20090146213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit'
[patent_app_type] => utility
[patent_app_number] => 12/318739
[patent_app_country] => US
[patent_app_date] => 2009-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 10346
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20090146213.pdf
[firstpage_image] =>[orig_patent_app_number] => 12318739
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/318739 | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit | Jan 6, 2009 | Issued |