Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5854495 [patent_doc_number] => 20060226428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Vertical gate device for an image sensor and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/447920 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4960 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226428.pdf [firstpage_image] =>[orig_patent_app_number] => 11447920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/447920
Vertical gate device for an image sensor and method of forming the same Jun 6, 2006 Abandoned
Array ( [id] => 5532594 [patent_doc_number] => 20090232382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => '\"IN VITRO\" DIAGNOSTIC METHOD FOR DISEASES AFFECTING HUMAN OR ANIMAL TISSUES' [patent_app_type] => utility [patent_app_number] => 12/303496 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7520 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20090232382.pdf [firstpage_image] =>[orig_patent_app_number] => 12303496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/303496
“In vitro” diagnostic method for diseases affecting human or animal tissues Jun 4, 2006 Issued
Array ( [id] => 4673449 [patent_doc_number] => 20080211077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Low profile chip scale stacking system and method' [patent_app_type] => utility [patent_app_number] => 11/432206 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7249 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211077.pdf [firstpage_image] =>[orig_patent_app_number] => 11432206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432206
Low profile chip scale stacking system and method May 10, 2006 Abandoned
Array ( [id] => 4997289 [patent_doc_number] => 20070039923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'METHOD FOR PREVENTING CHARGE-UP IN PLASMA PROCESS AND SEMICONDUCTOR WAFER MANUFACTURED USING SAME' [patent_app_type] => utility [patent_app_number] => 11/381218 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5313 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20070039923.pdf [firstpage_image] =>[orig_patent_app_number] => 11381218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381218
METHOD FOR PREVENTING CHARGE-UP IN PLASMA PROCESS AND SEMICONDUCTOR WAFER MANUFACTURED USING SAME May 1, 2006 Abandoned
Array ( [id] => 5622945 [patent_doc_number] => 20060261450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Leadframeless package structure and method' [patent_app_type] => utility [patent_app_number] => 11/410501 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3156 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261450.pdf [firstpage_image] =>[orig_patent_app_number] => 11410501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410501
Leadframeless package structure and method Apr 24, 2006 Abandoned
Array ( [id] => 5616942 [patent_doc_number] => 20060186474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/408181 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 18873 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186474.pdf [firstpage_image] =>[orig_patent_app_number] => 11408181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/408181
Semiconductor device and method of manufacturing the same Apr 20, 2006 Abandoned
Array ( [id] => 5628800 [patent_doc_number] => 20060145268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/367556 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5900 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145268.pdf [firstpage_image] =>[orig_patent_app_number] => 11367556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/367556
Semiconductor device and method for fabricating the same Mar 5, 2006 Abandoned
Array ( [id] => 5652942 [patent_doc_number] => 20060138677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Layered microelectronic contact and method for fabricating same' [patent_app_type] => utility [patent_app_number] => 11/362632 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9322 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138677.pdf [firstpage_image] =>[orig_patent_app_number] => 11362632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/362632
Layered microelectronic contact and method for fabricating same Feb 26, 2006 Abandoned
Array ( [id] => 587160 [patent_doc_number] => 07446363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material' [patent_app_type] => utility [patent_app_number] => 11/361111 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3316 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446363.pdf [firstpage_image] =>[orig_patent_app_number] => 11361111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361111
Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material Feb 23, 2006 Issued
Array ( [id] => 5617019 [patent_doc_number] => 20060186551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Flip chip package with advanced electrical and thermal properties for high current designs' [patent_app_type] => utility [patent_app_number] => 11/358668 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186551.pdf [firstpage_image] =>[orig_patent_app_number] => 11358668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358668
Flip chip package with advanced electrical and thermal properties for high current designs Feb 20, 2006 Issued
Array ( [id] => 5616930 [patent_doc_number] => 20060186462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Nonvolatile memory device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/357329 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186462.pdf [firstpage_image] =>[orig_patent_app_number] => 11357329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357329
Nonvolatile memory device and method of fabricating the same Feb 20, 2006 Abandoned
Array ( [id] => 5608761 [patent_doc_number] => 20060270277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Canted coil spring power terminal and sequence connection system' [patent_app_type] => utility [patent_app_number] => 11/356432 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270277.pdf [firstpage_image] =>[orig_patent_app_number] => 11356432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356432
Canted coil spring power terminal and sequence connection system Feb 15, 2006 Issued
Array ( [id] => 5619568 [patent_doc_number] => 20060189102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Process for treating substrates for the microelectronics industry, and substrates obtained by this process' [patent_app_type] => utility [patent_app_number] => 11/348502 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7304 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189102.pdf [firstpage_image] =>[orig_patent_app_number] => 11348502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348502
Process for treating substrates for the microelectronics industry, and substrates obtained by this process Feb 6, 2006 Issued
Array ( [id] => 229187 [patent_doc_number] => 07602002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Semiconductor device with DRAM portion having capacitor-over-bit-line structure and logic portion' [patent_app_type] => utility [patent_app_number] => 11/347370 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 10800 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602002.pdf [firstpage_image] =>[orig_patent_app_number] => 11347370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347370
Semiconductor device with DRAM portion having capacitor-over-bit-line structure and logic portion Feb 5, 2006 Issued
Array ( [id] => 5913034 [patent_doc_number] => 20060128096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Methods of forming semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/346870 [patent_app_country] => US [patent_app_date] => 2006-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9472 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128096.pdf [firstpage_image] =>[orig_patent_app_number] => 11346870 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346870
Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region Feb 1, 2006 Issued
Array ( [id] => 5869008 [patent_doc_number] => 20060163625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field' [patent_app_type] => utility [patent_app_number] => 11/341578 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7334 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163625.pdf [firstpage_image] =>[orig_patent_app_number] => 11341578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341578
Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field Jan 25, 2006 Abandoned
Array ( [id] => 5613990 [patent_doc_number] => 20060115918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Method for manufacturing a magnetic field detecting element' [patent_app_type] => utility [patent_app_number] => 11/336881 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20060115918.pdf [firstpage_image] =>[orig_patent_app_number] => 11336881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336881
Method for manufacturing a magnetic field detecting element Jan 22, 2006 Abandoned
Array ( [id] => 795861 [patent_doc_number] => 07429777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-30 [patent_title] => 'Semiconductor device with a gate electrode having a laminate structure' [patent_app_type] => utility [patent_app_number] => 11/329228 [patent_app_country] => US [patent_app_date] => 2006-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 8398 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/429/07429777.pdf [firstpage_image] =>[orig_patent_app_number] => 11329228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/329228
Semiconductor device with a gate electrode having a laminate structure Jan 10, 2006 Issued
Array ( [id] => 5619550 [patent_doc_number] => 20060189084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Memory element and memory device' [patent_app_type] => utility [patent_app_number] => 11/328049 [patent_app_country] => US [patent_app_date] => 2006-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9710 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20060189084.pdf [firstpage_image] =>[orig_patent_app_number] => 11328049 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/328049
Memory device comprising a memory layer and a metal chalcogenide ion-source layer Jan 8, 2006 Issued
Array ( [id] => 5652792 [patent_doc_number] => 20060138527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Semiconductor devices, and electronic systems comprising semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/324735 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9485 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138527.pdf [firstpage_image] =>[orig_patent_app_number] => 11324735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324735
Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer Dec 28, 2005 Issued
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