Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7228622 [patent_doc_number] => 20050269652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals' [patent_app_type] => utility [patent_app_number] => 11/200427 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5168 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269652.pdf [firstpage_image] =>[orig_patent_app_number] => 11200427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200427
NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals Aug 8, 2005 Issued
Array ( [id] => 7247973 [patent_doc_number] => 20050272206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals' [patent_app_type] => utility [patent_app_number] => 11/200334 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20050272206.pdf [firstpage_image] =>[orig_patent_app_number] => 11200334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200334
NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals Aug 8, 2005 Abandoned
Array ( [id] => 5765799 [patent_doc_number] => 20050263837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Bump style MEMS switch' [patent_app_type] => utility [patent_app_number] => 11/196994 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1390 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263837.pdf [firstpage_image] =>[orig_patent_app_number] => 11196994 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196994
Bump style MEMS switch Aug 3, 2005 Abandoned
Array ( [id] => 7228002 [patent_doc_number] => 20050269565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Semi-insulating bulk zinc oxide single crystal' [patent_app_type] => utility [patent_app_number] => 11/189218 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1667 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269565.pdf [firstpage_image] =>[orig_patent_app_number] => 11189218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/189218
Semi-insulating bulk zinc oxide single crystal Jul 24, 2005 Abandoned
Array ( [id] => 7045655 [patent_doc_number] => 20050250250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Diamond composite heat spreader having thermal conductivity gradients and associated methods' [patent_app_type] => utility [patent_app_number] => 11/179148 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250250.pdf [firstpage_image] =>[orig_patent_app_number] => 11179148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179148
Diamond composite heat spreader having thermal conductivity gradients and associated methods Jul 11, 2005 Issued
Array ( [id] => 7067001 [patent_doc_number] => 20050242383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Ferroelectric memory and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/175451 [patent_app_country] => US [patent_app_date] => 2005-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 31780 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242383.pdf [firstpage_image] =>[orig_patent_app_number] => 11175451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175451
Ferroelectric memory and method for manufacturing the same Jul 6, 2005 Abandoned
Array ( [id] => 7230137 [patent_doc_number] => 20050255689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers' [patent_app_type] => utility [patent_app_number] => 11/175869 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3409 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20050255689.pdf [firstpage_image] =>[orig_patent_app_number] => 11175869 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175869
Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers Jul 5, 2005 Abandoned
Array ( [id] => 5602402 [patent_doc_number] => 20060292747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Top-surface-mount power light emitter with integral heat sink' [patent_app_type] => utility [patent_app_number] => 11/168018 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3993 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292747.pdf [firstpage_image] =>[orig_patent_app_number] => 11168018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168018
Top-surface-mount power light emitter with integral heat sink Jun 26, 2005 Abandoned
Array ( [id] => 7213947 [patent_doc_number] => 20050253177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Two-transistor pixel with buried reset channel and method of formation' [patent_app_type] => utility [patent_app_number] => 11/157788 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4403 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253177.pdf [firstpage_image] =>[orig_patent_app_number] => 11157788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157788
Two-transistor pixel with buried reset channel and method of formation Jun 21, 2005 Abandoned
Array ( [id] => 6965118 [patent_doc_number] => 20050232015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Non-volatile semiconductor memory and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/156220 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5719 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20050232015.pdf [firstpage_image] =>[orig_patent_app_number] => 11156220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156220
Non-volatile semiconductor memory and manufacturing method thereof Jun 16, 2005 Abandoned
Array ( [id] => 6963366 [patent_doc_number] => 20050230263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Methods for forming interconnect structures by co-plating of noble metals and structures formed thereby' [patent_app_type] => utility [patent_app_number] => 11/152269 [patent_app_country] => US [patent_app_date] => 2005-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3336 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230263.pdf [firstpage_image] =>[orig_patent_app_number] => 11152269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152269
Methods for forming interconnect structures by co-plating of noble metals and structures formed thereby Jun 12, 2005 Abandoned
Array ( [id] => 5790778 [patent_doc_number] => 20060011910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'PCRAM device with switching glass layer' [patent_app_type] => utility [patent_app_number] => 11/146091 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6280 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20060011910.pdf [firstpage_image] =>[orig_patent_app_number] => 11146091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/146091
Memory device with switching glass layer Jun 6, 2005 Issued
Array ( [id] => 428966 [patent_doc_number] => 07268402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Memory cell with trench-isolated transistor including first and second isolation trenches' [patent_app_type] => utility [patent_app_number] => 11/119128 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3479 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268402.pdf [firstpage_image] =>[orig_patent_app_number] => 11119128 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/119128
Memory cell with trench-isolated transistor including first and second isolation trenches Apr 28, 2005 Issued
Array ( [id] => 7214075 [patent_doc_number] => 20050253195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Semiconductor device and image display device' [patent_app_type] => utility [patent_app_number] => 11/109818 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 23225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20050253195.pdf [firstpage_image] =>[orig_patent_app_number] => 11109818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/109818
Semiconductor device and image display device Apr 19, 2005 Abandoned
Array ( [id] => 6923717 [patent_doc_number] => 20050236972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Light emitting display (LED) and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/100639 [patent_app_country] => US [patent_app_date] => 2005-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4948 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20050236972.pdf [firstpage_image] =>[orig_patent_app_number] => 11100639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/100639
Light emitting display (LED) and method of manufacture Apr 6, 2005 Abandoned
Array ( [id] => 6949754 [patent_doc_number] => 20050224848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/097998 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 13866 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224848.pdf [firstpage_image] =>[orig_patent_app_number] => 11097998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097998
Trench-type power MOSFET with embedded region at the bottom of the gate and increased breakdown voltage Apr 3, 2005 Issued
Array ( [id] => 7002495 [patent_doc_number] => 20050167808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor device, its fabrication method and electronic device' [patent_app_type] => utility [patent_app_number] => 11/092685 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11421 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167808.pdf [firstpage_image] =>[orig_patent_app_number] => 11092685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092685
Semiconductor device, its fabrication method and electronic device Mar 29, 2005 Abandoned
Array ( [id] => 522481 [patent_doc_number] => 07190058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Spacer die structure and method for attaching' [patent_app_type] => utility [patent_app_number] => 11/087375 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 22 [patent_no_of_words] => 3530 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190058.pdf [firstpage_image] =>[orig_patent_app_number] => 11087375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/087375
Spacer die structure and method for attaching Mar 22, 2005 Issued
Array ( [id] => 6963775 [patent_doc_number] => 20050230672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'III-V compound semiconductor crystals' [patent_app_type] => utility [patent_app_number] => 11/084169 [patent_app_country] => US [patent_app_date] => 2005-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8048 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230672.pdf [firstpage_image] =>[orig_patent_app_number] => 11084169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/084169
III-V compound semiconductor crystals Mar 20, 2005 Abandoned
Array ( [id] => 5683038 [patent_doc_number] => 20060199308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Process for manufacturing sawing type leadless semiconductor packages' [patent_app_type] => utility [patent_app_number] => 11/068799 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2249 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199308.pdf [firstpage_image] =>[orig_patent_app_number] => 11068799 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068799
Process for manufacturing sawing type leadless semiconductor packages Mar 1, 2005 Abandoned
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