
Marcos D. Pizarro Crespo
Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 1073 |
| Issued Applications | 704 |
| Pending Applications | 106 |
| Abandoned Applications | 293 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5790847
[patent_doc_number] => 20060011951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Process for fabricating non-volatile memory by tilt-angle ion implantation'
[patent_app_type] => utility
[patent_app_number] => 10/891569
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5179
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20060011951.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891569
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891569 | Method for forming potassium/sodium ion sensing device applying extended-gate field effect transistor | Jul 14, 2004 | Issued |
Array
(
[id] => 484432
[patent_doc_number] => 07221031
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Semiconductor device having sufficient process margin and method of forming same'
[patent_app_type] => utility
[patent_app_number] => 10/892588
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 33
[patent_no_of_words] => 6022
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/221/07221031.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892588
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892588 | Semiconductor device having sufficient process margin and method of forming same | Jul 14, 2004 | Issued |
Array
(
[id] => 5790910
[patent_doc_number] => 20060011985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)'
[patent_app_type] => utility
[patent_app_number] => 10/893519
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5824
[patent_no_of_claims] => 53
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20060011985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10893519
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/893519 | Asymmetric hetero-doped high-voltage MOSFET (AH2MOS) | Jul 14, 2004 | Issued |
Array
(
[id] => 7125164
[patent_doc_number] => 20050056908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/892459
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 7418
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20050056908.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892459
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892459 | Semiconductor device including transistors having different drain breakdown voltages on a single substrate | Jul 14, 2004 | Issued |
Array
(
[id] => 817481
[patent_doc_number] => 07411289
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-08-12
[patent_title] => 'Integrated circuit package with partially exposed contact pads and process for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/891709
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 45
[patent_no_of_words] => 3788
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/411/07411289.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891709
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891709 | Integrated circuit package with partially exposed contact pads and process for fabricating the same | Jul 14, 2004 | Issued |
Array
(
[id] => 534037
[patent_doc_number] => 07176073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Methods of forming memory cells having diodes and electrode plates connected to source/drain regions'
[patent_app_type] => utility
[patent_app_number] => 10/892340
[patent_app_country] => US
[patent_app_date] => 2004-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 31
[patent_no_of_words] => 13536
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/176/07176073.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892340
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892340 | Methods of forming memory cells having diodes and electrode plates connected to source/drain regions | Jul 13, 2004 | Issued |
Array
(
[id] => 7234889
[patent_doc_number] => 20040256669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Distributed power MOSFET'
[patent_app_type] => new
[patent_app_number] => 10/888776
[patent_app_country] => US
[patent_app_date] => 2004-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7128
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20040256669.pdf
[firstpage_image] =>[orig_patent_app_number] => 10888776
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/888776 | Distributed power MOSFET | Jul 8, 2004 | Issued |
Array
(
[id] => 6975523
[patent_doc_number] => 20050285238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Integrated transistor module and method of fabricating same'
[patent_app_type] => utility
[patent_app_number] => 10/876248
[patent_app_country] => US
[patent_app_date] => 2004-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2629
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20050285238.pdf
[firstpage_image] =>[orig_patent_app_number] => 10876248
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/876248 | Integrated transistor module and method of fabricating same | Jun 23, 2004 | Issued |
Array
(
[id] => 7407572
[patent_doc_number] => 20040227244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Passivated magneto-resistive bit structure'
[patent_app_type] => new
[patent_app_number] => 10/873363
[patent_app_country] => US
[patent_app_date] => 2004-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2685
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0227/20040227244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10873363
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/873363 | Passivated magneto-resistive bit structure | Jun 20, 2004 | Abandoned |
Array
(
[id] => 620441
[patent_doc_number] => 07141858
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-28
[patent_title] => 'Dual work function CMOS gate technology based on metal interdiffusion'
[patent_app_type] => utility
[patent_app_number] => 10/871338
[patent_app_country] => US
[patent_app_date] => 2004-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 3031
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/141/07141858.pdf
[firstpage_image] =>[orig_patent_app_number] => 10871338
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/871338 | Dual work function CMOS gate technology based on metal interdiffusion | Jun 17, 2004 | Issued |
Array
(
[id] => 7314300
[patent_doc_number] => 20040222481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Imager light shield'
[patent_app_type] => new
[patent_app_number] => 10/869868
[patent_app_country] => US
[patent_app_date] => 2004-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 4989
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20040222481.pdf
[firstpage_image] =>[orig_patent_app_number] => 10869868
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869868 | Imager light shield | Jun 17, 2004 | Issued |
Array
(
[id] => 645224
[patent_doc_number] => 07118973
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-10
[patent_title] => 'Method of forming a transistor with a channel region in a layer of composite material'
[patent_app_type] => utility
[patent_app_number] => 10/869158
[patent_app_country] => US
[patent_app_date] => 2004-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2312
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/118/07118973.pdf
[firstpage_image] =>[orig_patent_app_number] => 10869158
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869158 | Method of forming a transistor with a channel region in a layer of composite material | Jun 15, 2004 | Issued |
Array
(
[id] => 7349569
[patent_doc_number] => 20040248478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Organic EL device and method for its manufacture'
[patent_app_type] => new
[patent_app_number] => 10/869728
[patent_app_country] => US
[patent_app_date] => 2004-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4130
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20040248478.pdf
[firstpage_image] =>[orig_patent_app_number] => 10869728
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869728 | Organic EL device and method for its manufacture | Jun 15, 2004 | Abandoned |
Array
(
[id] => 877567
[patent_doc_number] => 07358608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-15
[patent_title] => 'Semiconductor device having chip size package with improved strength'
[patent_app_type] => utility
[patent_app_number] => 10/866189
[patent_app_country] => US
[patent_app_date] => 2004-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2504
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/358/07358608.pdf
[firstpage_image] =>[orig_patent_app_number] => 10866189
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/866189 | Semiconductor device having chip size package with improved strength | Jun 13, 2004 | Issued |
Array
(
[id] => 7053914
[patent_doc_number] => 20050275086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Semiconductor package and process utilizing pre-formed mold cap and heatspreader assembly'
[patent_app_type] => utility
[patent_app_number] => 10/865179
[patent_app_country] => US
[patent_app_date] => 2004-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2675
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0275/20050275086.pdf
[firstpage_image] =>[orig_patent_app_number] => 10865179
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/865179 | Semiconductor package and process utilizing pre-formed mold cap and heatspreader assembly | Jun 8, 2004 | Issued |
Array
(
[id] => 7423733
[patent_doc_number] => 20040229451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'Method and structure for tungsten gate metal surface treatment while preventing oxidation'
[patent_app_type] => new
[patent_app_number] => 10/862990
[patent_app_country] => US
[patent_app_date] => 2004-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1847
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 3
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20040229451.pdf
[firstpage_image] =>[orig_patent_app_number] => 10862990
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/862990 | Method and structure for tungsten gate metal surface treatment while preventing oxidation | Jun 7, 2004 | Issued |
Array
(
[id] => 7317818
[patent_doc_number] => 20040224439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof and a method of fabricating the semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/859569
[patent_app_country] => US
[patent_app_date] => 2004-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3399
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20040224439.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859569
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859569 | Semiconductor package including a double-faced semiconductor chip having integrated circuitry on both sides thereof and a method of fabricating the semiconductor package | Jun 2, 2004 | Abandoned |
Array
(
[id] => 7058944
[patent_doc_number] => 20050001303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method of manufacturing multi-chip stacking package'
[patent_app_type] => utility
[patent_app_number] => 10/859279
[patent_app_country] => US
[patent_app_date] => 2004-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1623
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20050001303.pdf
[firstpage_image] =>[orig_patent_app_number] => 10859279
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/859279 | Method of manufacturing multi-chip stacking package | Jun 1, 2004 | Abandoned |
Array
(
[id] => 7086621
[patent_doc_number] => 20050006733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Lead frame and semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 10/853148
[patent_app_country] => US
[patent_app_date] => 2004-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 7501
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20050006733.pdf
[firstpage_image] =>[orig_patent_app_number] => 10853148
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/853148 | Lead frame and semiconductor device using the same | May 25, 2004 | Abandoned |
Array
(
[id] => 514910
[patent_doc_number] => 07192839
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-20
[patent_title] => 'Semiconductor structure having alignment marks with shallow trench isolation'
[patent_app_type] => utility
[patent_app_number] => 10/848638
[patent_app_country] => US
[patent_app_date] => 2004-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4286
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/192/07192839.pdf
[firstpage_image] =>[orig_patent_app_number] => 10848638
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/848638 | Semiconductor structure having alignment marks with shallow trench isolation | May 18, 2004 | Issued |