
Marcos D. Pizarro Crespo
Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 1073 |
| Issued Applications | 704 |
| Pending Applications | 106 |
| Abandoned Applications | 293 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 480260
[patent_doc_number] => 07224073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-29
[patent_title] => 'Substrate for solder joint'
[patent_app_type] => utility
[patent_app_number] => 10/848649
[patent_app_country] => US
[patent_app_date] => 2004-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3981
[patent_no_of_claims] => 9
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[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/224/07224073.pdf
[firstpage_image] =>[orig_patent_app_number] => 10848649
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/848649 | Substrate for solder joint | May 17, 2004 | Issued |
Array
(
[id] => 7043350
[patent_doc_number] => 20050247945
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'LED heat-radiating substrate and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/841639
[patent_app_country] => US
[patent_app_date] => 2004-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 1958
[patent_no_of_claims] => 29
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0247/20050247945.pdf
[firstpage_image] =>[orig_patent_app_number] => 10841639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841639 | LED heat-radiating substrate and method for making the same | May 9, 2004 | Abandoned |
Array
(
[id] => 443691
[patent_doc_number] => 07256463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-14
[patent_title] => 'Semiconductor device having SOI structure including a load resistor of an sram memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/841469
[patent_app_country] => US
[patent_app_date] => 2004-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 59
[patent_no_of_words] => 18941
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 181
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/256/07256463.pdf
[firstpage_image] =>[orig_patent_app_number] => 10841469
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841469 | Semiconductor device having SOI structure including a load resistor of an sram memory cell | May 9, 2004 | Issued |
Array
(
[id] => 7314240
[patent_doc_number] => 20040222440
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Chip scale package with flip chip interconnect'
[patent_app_type] => new
[patent_app_number] => 10/838639
[patent_app_country] => US
[patent_app_date] => 2004-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3849
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20040222440.pdf
[firstpage_image] =>[orig_patent_app_number] => 10838639
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/838639 | Chip scale package with flip chip interconnect | May 3, 2004 | Abandoned |
Array
(
[id] => 7170114
[patent_doc_number] => 20040200062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Leadframeless package structure and method'
[patent_app_type] => new
[patent_app_number] => 10/835419
[patent_app_country] => US
[patent_app_date] => 2004-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3192
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20040200062.pdf
[firstpage_image] =>[orig_patent_app_number] => 10835419
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/835419 | Leadframeless package structure and method | Apr 28, 2004 | Abandoned |
Array
(
[id] => 7184183
[patent_doc_number] => 20040203209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Methods of forming field effect transistors including floating gate field effect transistors'
[patent_app_type] => new
[patent_app_number] => 10/837428
[patent_app_country] => US
[patent_app_date] => 2004-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3031
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20040203209.pdf
[firstpage_image] =>[orig_patent_app_number] => 10837428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/837428 | Methods of forming field effect transistors including floating gate field effect transistors | Apr 28, 2004 | Issued |
Array
(
[id] => 7442340
[patent_doc_number] => 20040195694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'BEOL decoupling capacitor'
[patent_app_type] => new
[patent_app_number] => 10/830798
[patent_app_country] => US
[patent_app_date] => 2004-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4176
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0195/20040195694.pdf
[firstpage_image] =>[orig_patent_app_number] => 10830798
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/830798 | BEOL decoupling capacitor | Apr 22, 2004 | Abandoned |
Array
(
[id] => 7441285
[patent_doc_number] => 20040195592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Two-transistor pixel with buried reset channel and method of formation'
[patent_app_type] => new
[patent_app_number] => 10/827379
[patent_app_country] => US
[patent_app_date] => 2004-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4452
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0195/20040195592.pdf
[firstpage_image] =>[orig_patent_app_number] => 10827379
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/827379 | Two-transistor pixel with buried reset channel and method of formation | Apr 19, 2004 | Issued |
Array
(
[id] => 7462231
[patent_doc_number] => 20040197959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/825678
[patent_app_country] => US
[patent_app_date] => 2004-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[patent_no_of_words] => 11898
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[pdf_file] => publications/A1/0197/20040197959.pdf
[firstpage_image] =>[orig_patent_app_number] => 10825678
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/825678 | Semiconductor device and method of manufacturing the same | Apr 15, 2004 | Abandoned |
Array
(
[id] => 536275
[patent_doc_number] => 07180193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Via recess in underlying conductive line'
[patent_app_type] => utility
[patent_app_number] => 10/823159
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3246
[patent_no_of_claims] => 27
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/180/07180193.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823159
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823159 | Via recess in underlying conductive line | Apr 12, 2004 | Issued |
Array
(
[id] => 7174242
[patent_doc_number] => 20040201078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Field plate structure for high voltage devices'
[patent_app_type] => new
[patent_app_number] => 10/823298
[patent_app_country] => US
[patent_app_date] => 2004-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20040201078.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823298
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823298 | Field plate structure for high voltage devices | Apr 11, 2004 | Abandoned |
Array
(
[id] => 6949898
[patent_doc_number] => 20050224992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'METHOD AND APPARATUS TO ELIMINATE GALVANIC CORROSION ON COPPER DOPED ALUMINUM BOND PADS ON INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 10/817619
[patent_app_country] => US
[patent_app_date] => 2004-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2005
[patent_no_of_claims] => 18
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[pdf_file] => publications/A1/0224/20050224992.pdf
[firstpage_image] =>[orig_patent_app_number] => 10817619
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/817619 | Method and apparatus to eliminate galvanic corrosion on copper doped aluminum bond pads on integrated circuits | Mar 31, 2004 | Issued |
Array
(
[id] => 730193
[patent_doc_number] => 07042096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Single semiconductor element in a flip chip construction'
[patent_app_type] => utility
[patent_app_number] => 10/817338
[patent_app_country] => US
[patent_app_date] => 2004-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/07/042/07042096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10817338
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/817338 | Single semiconductor element in a flip chip construction | Mar 31, 2004 | Issued |
Array
(
[id] => 548317
[patent_doc_number] => 07164189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-16
[patent_title] => 'Slim spacer device and manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/816089
[patent_app_country] => US
[patent_app_date] => 2004-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/164/07164189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10816089
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/816089 | Slim spacer device and manufacturing method | Mar 30, 2004 | Issued |
Array
(
[id] => 509540
[patent_doc_number] => 07195953
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein'
[patent_app_type] => utility
[patent_app_number] => 10/811999
[patent_app_country] => US
[patent_app_date] => 2004-03-30
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[pdf_file] => patents/07/195/07195953.pdf
[firstpage_image] =>[orig_patent_app_number] => 10811999
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/811999 | Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein | Mar 29, 2004 | Issued |
Array
(
[id] => 443665
[patent_doc_number] => 07256450
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-14
[patent_title] => 'NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals'
[patent_app_type] => utility
[patent_app_number] => 10/808059
[patent_app_country] => US
[patent_app_date] => 2004-03-24
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[pdf_file] => patents/07/256/07256450.pdf
[firstpage_image] =>[orig_patent_app_number] => 10808059
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/808059 | NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals | Mar 23, 2004 | Issued |
Array
(
[id] => 7363376
[patent_doc_number] => 20040217468
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[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Semiconductor chip, semiconductor device, method of manufacturing the same, circuit board, and electronic equipment'
[patent_app_type] => new
[patent_app_number] => 10/807438
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0217/20040217468.pdf
[firstpage_image] =>[orig_patent_app_number] => 10807438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/807438 | Semiconductor device having a plurality of stacked semiconductor chips with positions of chip-selecting terminals being different from each other | Mar 23, 2004 | Issued |
Array
(
[id] => 7089097
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[patent_title] => 'Magnetic random access memory and method of manufacturing the same'
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[firstpage_image] =>[orig_patent_app_number] => 10806388
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/806388 | Magnetic random access memory and method of manufacturing the same | Mar 22, 2004 | Abandoned |
Array
(
[id] => 7375581
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[patent_title] => 'Multilayer circuit and method of manufacturing'
[patent_app_type] => new
[patent_app_number] => 10/806269
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10806269
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/806269 | Multilayer circuit including stacked layers of insulating material and conductive sections | Mar 22, 2004 | Issued |
Array
(
[id] => 7108516
[patent_doc_number] => 20050205969
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Charge trap non-volatile memory structure for 2 bits per transistor'
[patent_app_type] => utility
[patent_app_number] => 10/805158
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0205/20050205969.pdf
[firstpage_image] =>[orig_patent_app_number] => 10805158
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/805158 | Charge trap non-volatile memory structure for 2 bits per transistor | Mar 18, 2004 | Abandoned |