Marcos D. Pizarro Crespo

Array ( [id] => 1206941 [patent_doc_number] => 06717184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Light-emitting element array having an element separating region' [patent_app_type] => B2 [patent_app_number] => 10/253730 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717184.pdf [firstpage_image] =>[orig_patent_app_number] => 10253730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1037499 [patent_doc_number] => 06872648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Reduced splattering of unpassivated laser fuses' [patent_app_type] => utility [patent_app_number] => 10/246999 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4921 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872648.pdf [firstpage_image] =>[orig_patent_app_number] => 10246999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6718635 [patent_doc_number] => 20030052322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Nitride-based semiconductor light-emitting device and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/244448 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10460 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052322.pdf [firstpage_image] =>[orig_patent_app_number] => 10244448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1158444 [patent_doc_number] => 06765262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Vertical high-voltage semiconductor component' [patent_app_type] => B2 [patent_app_number] => 10/244789 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765262.pdf [firstpage_image] =>[orig_patent_app_number] => 10244789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6718689 [patent_doc_number] => 20030052376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Semiconductor device with high-k dielectric layer and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/241939 [patent_app_country] => US [patent_app_date] => 2002-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7308 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052376.pdf [firstpage_image] =>[orig_patent_app_number] => 10241939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 779598 [patent_doc_number] => 06995453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'High voltage integrated circuit including bipolar transistor within high voltage island area' [patent_app_type] => utility [patent_app_number] => 10/241818 [patent_app_country] => US [patent_app_date] => 2002-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2293 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995453.pdf [firstpage_image] =>[orig_patent_app_number] => 10241818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525912 [patent_doc_number] => 07187035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 10/237206 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 24 [patent_no_of_words] => 8290 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187035.pdf [firstpage_image] =>[orig_patent_app_number] => 10237206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6776702 [patent_doc_number] => 20030047782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Complementary MOS semiconductor device' [patent_app_type] => new [patent_app_number] => 10/234878 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10618 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20030047782.pdf [firstpage_image] =>[orig_patent_app_number] => 10234878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525847 [patent_doc_number] => 07187029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Nonvolatile semiconductor memory device with floating gate and two control gates' [patent_app_type] => utility [patent_app_number] => 10/230369 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 76 [patent_no_of_words] => 8983 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187029.pdf [firstpage_image] =>[orig_patent_app_number] => 10230369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7135111 [patent_doc_number] => 20040043561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Double-doped polysilicon floating gate' [patent_app_type] => new [patent_app_number] => 10/230523 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5612 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043561.pdf [firstpage_image] =>[orig_patent_app_number] => 10230523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1085643 [patent_doc_number] => 06830988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-14 [patent_title] => 'Method of forming an isolation structure for an integrated circuit utilizing grown and deposited oxide' [patent_app_type] => B1 [patent_app_number] => 10/228769 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2633 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/830/06830988.pdf [firstpage_image] =>[orig_patent_app_number] => 10228769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7130168 [patent_doc_number] => 20040041197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Hexagonal gate structure for radiation resistant flash memory cell' [patent_app_type] => new [patent_app_number] => 10/064882 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2274 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041197.pdf [firstpage_image] =>[orig_patent_app_number] => 10064882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547557 [patent_doc_number] => 07166896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Cross diffusion barrier layer in polysilicon' [patent_app_type] => utility [patent_app_number] => 10/228839 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 4609 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166896.pdf [firstpage_image] =>[orig_patent_app_number] => 10228839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6854181 [patent_doc_number] => 20030127682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Non-volatile memory device having improved coupling ratio uniformity' [patent_app_type] => new [patent_app_number] => 10/222109 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3732 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20030127682.pdf [firstpage_image] =>[orig_patent_app_number] => 10222109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494545 [patent_doc_number] => 20020190358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Deformation-absorbing leadframe for semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/212924 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4002 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190358.pdf [firstpage_image] =>[orig_patent_app_number] => 10212924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494647 [patent_doc_number] => 20020190369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Semiconductor chip, chip-on-chip structure device, and assembling method thereof' [patent_app_type] => new [patent_app_number] => 10/211308 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12311 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190369.pdf [firstpage_image] =>[orig_patent_app_number] => 10211308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6647158 [patent_doc_number] => 20030075789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Semiconductor storage device having memory chips in a stacked structure' [patent_app_type] => new [patent_app_number] => 10/197901 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15908 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20030075789.pdf [firstpage_image] =>[orig_patent_app_number] => 10197901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1188812 [patent_doc_number] => 06734043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Pressure-bonded heat sink method' [patent_app_type] => B2 [patent_app_number] => 10/196147 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734043.pdf [firstpage_image] =>[orig_patent_app_number] => 10196147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6733366 [patent_doc_number] => 20030011001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Process for selective epitaxial growth and bipolar transistor made by using such process' [patent_app_type] => new [patent_app_number] => 10/194053 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1818 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20030011001.pdf [firstpage_image] =>[orig_patent_app_number] => 10194053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7421129 [patent_doc_number] => 20040000689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Dual-bit MONOS/SONOS memory structure with non-continuous floating gate' [patent_app_type] => new [patent_app_number] => 10/183528 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2063 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20040000689.pdf [firstpage_image] =>[orig_patent_app_number] => 10183528 [rel_patent_id] =>[rel_patent_doc_number] =>)