Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5798534 [patent_doc_number] => 20020008275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Nonvolatile semiconductor memory device and its manufacture' [patent_app_type] => new [patent_app_number] => 09/885968 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008275.pdf [firstpage_image] =>[orig_patent_app_number] => 09885968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885968
Method of manufacturing a nonvolatile semiconductor memory device Jun 21, 2001 Issued
Array ( [id] => 951596 [patent_doc_number] => 06960801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'High density single transistor ferroelectric non-volatile memory' [patent_app_type] => utility [patent_app_number] => 09/882480 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3292 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960801.pdf [firstpage_image] =>[orig_patent_app_number] => 09882480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882480
High density single transistor ferroelectric non-volatile memory Jun 13, 2001 Issued
Array ( [id] => 5997112 [patent_doc_number] => 20020027245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Field effect transistor with reduced narrow channel effect' [patent_app_type] => new [patent_app_number] => 09/878339 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027245.pdf [firstpage_image] =>[orig_patent_app_number] => 09878339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878339
Field effect transistor with reduced narrow channel effect Jun 11, 2001 Issued
Array ( [id] => 7631033 [patent_doc_number] => 06635899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Semiconductor element having microcrystalline grains and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/839891 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 14696 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635899.pdf [firstpage_image] =>[orig_patent_app_number] => 09839891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/839891
Semiconductor element having microcrystalline grains and manufacturing method thereof Apr 22, 2001 Issued
Array ( [id] => 6886609 [patent_doc_number] => 20010019878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/824688 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3971 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019878.pdf [firstpage_image] =>[orig_patent_app_number] => 09824688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824688
Metal-gettering method used in the manufacture of crystalline-Si TFT Apr 3, 2001 Issued
Array ( [id] => 6961310 [patent_doc_number] => 20010012658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Method for producing a semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/826231 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3649 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012658.pdf [firstpage_image] =>[orig_patent_app_number] => 09826231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826231
Method for producing a semiconductor memory device with a multiplicity of memory cells Apr 3, 2001 Issued
Array ( [id] => 7093119 [patent_doc_number] => 20010034085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Method of manufacturing a semiconductor and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/820658 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10216 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034085.pdf [firstpage_image] =>[orig_patent_app_number] => 09820658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820658
Process for fabricating a aligned LDD transistor Mar 29, 2001 Issued
Array ( [id] => 7028148 [patent_doc_number] => 20010014500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Method of forming retrograde doping profile in twin well CMOS device' [patent_app_type] => new [patent_app_number] => 09/811590 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3844 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014500.pdf [firstpage_image] =>[orig_patent_app_number] => 09811590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811590
Method of forming retrograde doping file in twin well CMOS device Mar 19, 2001 Issued
Array ( [id] => 6888487 [patent_doc_number] => 20010023942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Semiconductor device of heterojunction structure having quantum dot buffer layer' [patent_app_type] => new [patent_app_number] => 09/809934 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2265 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023942.pdf [firstpage_image] =>[orig_patent_app_number] => 09809934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809934
Semiconductor device of heterojunction structure having quantum dot buffer layer Mar 15, 2001 Abandoned
Array ( [id] => 991106 [patent_doc_number] => 06919633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Multi-section foldable memory device' [patent_app_type] => utility [patent_app_number] => 09/800939 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6281 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919633.pdf [firstpage_image] =>[orig_patent_app_number] => 09800939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800939
Multi-section foldable memory device Mar 6, 2001 Issued
Array ( [id] => 6893087 [patent_doc_number] => 20010015453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'CAPACITOR FORMING METHODS' [patent_app_type] => new [patent_app_number] => 09/797899 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3286 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015453.pdf [firstpage_image] =>[orig_patent_app_number] => 09797899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797899
Methods of forming a capacitor with an amorphous and a crystalline high K capacitor dielectric region Feb 28, 2001 Issued
Array ( [id] => 1349530 [patent_doc_number] => 06572461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method for producing wafer notches with rounded corners and a tool therefor' [patent_app_type] => B2 [patent_app_number] => 09/781446 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2107 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/572/06572461.pdf [firstpage_image] =>[orig_patent_app_number] => 09781446 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781446
Method for producing wafer notches with rounded corners and a tool therefor Feb 12, 2001 Issued
Array ( [id] => 1360870 [patent_doc_number] => 06577009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Use of sic for preventing copper contamination of dielectric layer' [patent_app_type] => B1 [patent_app_number] => 09/776718 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 10108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/577/06577009.pdf [firstpage_image] =>[orig_patent_app_number] => 09776718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776718
Use of sic for preventing copper contamination of dielectric layer Feb 5, 2001 Issued
Array ( [id] => 1602603 [patent_doc_number] => 06432782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => '8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate' [patent_app_type] => B1 [patent_app_number] => 09/776290 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2905 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432782.pdf [firstpage_image] =>[orig_patent_app_number] => 09776290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776290
8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate Feb 1, 2001 Issued
Array ( [id] => 7117919 [patent_doc_number] => 20010001488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer' [patent_app_type] => new-utility [patent_app_number] => 09/759128 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001488.pdf [firstpage_image] =>[orig_patent_app_number] => 09759128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759128
Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer Jan 10, 2001 Issued
Array ( [id] => 6893082 [patent_doc_number] => 20010015448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Ferroelectric capacitor and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/749788 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015448.pdf [firstpage_image] =>[orig_patent_app_number] => 09749788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749788
Ferroelectric capacitor and semiconductor device Dec 27, 2000 Abandoned
Array ( [id] => 7014598 [patent_doc_number] => 20010051436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Fabrication method and structure for ferroelectric nonvolatile memory field effect transistor' [patent_app_type] => new [patent_app_number] => 09/747779 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3166 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051436.pdf [firstpage_image] =>[orig_patent_app_number] => 09747779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747779
Fabrication method and structure for ferroelectric nonvolatile memory field effect transistor Dec 21, 2000 Issued
Array ( [id] => 1419751 [patent_doc_number] => 06525426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Subresolution features for a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/738419 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5221 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525426.pdf [firstpage_image] =>[orig_patent_app_number] => 09738419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738419
Subresolution features for a semiconductor device Dec 14, 2000 Issued
Array ( [id] => 5825895 [patent_doc_number] => 20020066923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Non-volatile flash memory cell with short floating gate' [patent_app_type] => new [patent_app_number] => 09/729829 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066923.pdf [firstpage_image] =>[orig_patent_app_number] => 09729829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729829
Non-volatile flash memory cell with short floating gate Dec 5, 2000 Abandoned
Array ( [id] => 1221721 [patent_doc_number] => 06703669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Semiconductor device having serially connected memory cell transistors provided between two current terminals' [patent_app_type] => B1 [patent_app_number] => 09/714228 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 5139 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703669.pdf [firstpage_image] =>[orig_patent_app_number] => 09714228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714228
Semiconductor device having serially connected memory cell transistors provided between two current terminals Nov 16, 2000 Issued
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