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Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1321508 [patent_doc_number] => 06605850 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-12 [patent_title] => 'Solid-state image pickup device using layers having different refractive indices' [patent_app_type] => B1 [patent_app_number] => 09/706860 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4446 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605850.pdf [firstpage_image] =>[orig_patent_app_number] => 09706860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706860
Solid-state image pickup device using layers having different refractive indices Nov 6, 2000 Issued
Array ( [id] => 1297387 [patent_doc_number] => 06627508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method of forming capacitors containing tantalum' [patent_app_type] => B1 [patent_app_number] => 09/684069 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2914 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627508.pdf [firstpage_image] =>[orig_patent_app_number] => 09684069 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684069
Method of forming capacitors containing tantalum Oct 5, 2000 Issued
Array ( [id] => 1490148 [patent_doc_number] => 06417047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Manufacturing method of a non-volatile semiconductor memory device having isolation regions' [patent_app_type] => B1 [patent_app_number] => 09/665689 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6356 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 507 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417047.pdf [firstpage_image] =>[orig_patent_app_number] => 09665689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/665689
Manufacturing method of a non-volatile semiconductor memory device having isolation regions Sep 19, 2000 Issued
Array ( [id] => 1375210 [patent_doc_number] => 06566760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor storage device having memory chips in a stacked structure' [patent_app_type] => B1 [patent_app_number] => 09/666063 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 15783 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566760.pdf [firstpage_image] =>[orig_patent_app_number] => 09666063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666063
Semiconductor storage device having memory chips in a stacked structure Sep 18, 2000 Issued
Array ( [id] => 1458788 [patent_doc_number] => 06426266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Manufacturing method for an inverted-structure bipolar transistor with improved high-frequency characteristics' [patent_app_type] => B1 [patent_app_number] => 09/661802 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 6647 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426266.pdf [firstpage_image] =>[orig_patent_app_number] => 09661802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661802
Manufacturing method for an inverted-structure bipolar transistor with improved high-frequency characteristics Sep 13, 2000 Issued
Array ( [id] => 1459282 [patent_doc_number] => 06391693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for making polysilicon thin film transistor having multiple gate electrodes' [patent_app_type] => B1 [patent_app_number] => 09/652187 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2021 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391693.pdf [firstpage_image] =>[orig_patent_app_number] => 09652187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652187
Method for making polysilicon thin film transistor having multiple gate electrodes Aug 30, 2000 Issued
Array ( [id] => 996577 [patent_doc_number] => 06914017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Residue free overlay target' [patent_app_type] => utility [patent_app_number] => 09/651790 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 3972 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914017.pdf [firstpage_image] =>[orig_patent_app_number] => 09651790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651790
Residue free overlay target Aug 29, 2000 Issued
Array ( [id] => 1300044 [patent_doc_number] => 06627947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Compact single-poly two transistor EEPROM cell' [patent_app_type] => B1 [patent_app_number] => 09/643279 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3618 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627947.pdf [firstpage_image] =>[orig_patent_app_number] => 09643279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643279
Compact single-poly two transistor EEPROM cell Aug 21, 2000 Issued
Array ( [id] => 741003 [patent_doc_number] => 07029993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method for treating substrates for microelectronics and substrates obtained according to said method' [patent_app_type] => utility [patent_app_number] => 10/069058 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7261 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/029/07029993.pdf [firstpage_image] =>[orig_patent_app_number] => 10069058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/069058
Method for treating substrates for microelectronics and substrates obtained according to said method Aug 16, 2000 Issued
Array ( [id] => 1463711 [patent_doc_number] => 06392922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Passivated magneto-resistive bit structure and passivation method therefor' [patent_app_type] => B1 [patent_app_number] => 09/638419 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2559 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392922.pdf [firstpage_image] =>[orig_patent_app_number] => 09638419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638419
Passivated magneto-resistive bit structure and passivation method therefor Aug 13, 2000 Issued
09/635818 Laminated type semiconductor ceramic element and production method for the laminated type semiconductor ceramic element Aug 8, 2000 Abandoned
Array ( [id] => 1505369 [patent_doc_number] => 06465838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Surrounding-gate flash memory having a self-aligned control gate' [patent_app_type] => B1 [patent_app_number] => 09/630868 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4481 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465838.pdf [firstpage_image] =>[orig_patent_app_number] => 09630868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630868
Surrounding-gate flash memory having a self-aligned control gate Aug 1, 2000 Issued
Array ( [id] => 1155591 [patent_doc_number] => 06764904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings' [patent_app_type] => B1 [patent_app_number] => 09/629780 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4324 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764904.pdf [firstpage_image] =>[orig_patent_app_number] => 09629780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629780
Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings Jul 30, 2000 Issued
Array ( [id] => 1561090 [patent_doc_number] => 06362046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor device allowing electrical writing and erasing of information and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/618764 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 8338 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362046.pdf [firstpage_image] =>[orig_patent_app_number] => 09618764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618764
Semiconductor device allowing electrical writing and erasing of information and method of manufacturing the same Jul 17, 2000 Issued
Array ( [id] => 1542524 [patent_doc_number] => 06372568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of manufacture of a semiconductor having a triple well structure' [patent_app_type] => B1 [patent_app_number] => 09/615529 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2505 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372568.pdf [firstpage_image] =>[orig_patent_app_number] => 09615529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615529
Method of manufacture of a semiconductor having a triple well structure Jul 12, 2000 Issued
Array ( [id] => 1440986 [patent_doc_number] => 06495876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS' [patent_app_type] => B1 [patent_app_number] => 09/609288 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495876.pdf [firstpage_image] =>[orig_patent_app_number] => 09609288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609288
DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS Jun 29, 2000 Issued
Array ( [id] => 1459964 [patent_doc_number] => 06426560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor device and memory module' [patent_app_type] => B1 [patent_app_number] => 09/608149 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 15762 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426560.pdf [firstpage_image] =>[orig_patent_app_number] => 09608149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608149
Semiconductor device and memory module Jun 29, 2000 Issued
Array ( [id] => 7643561 [patent_doc_number] => 06429480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor device having nonvolatile memory cell and field effect transistor' [patent_app_type] => B1 [patent_app_number] => 09/605738 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6117 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429480.pdf [firstpage_image] =>[orig_patent_app_number] => 09605738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605738
Semiconductor device having nonvolatile memory cell and field effect transistor Jun 28, 2000 Issued
Array ( [id] => 1452304 [patent_doc_number] => 06455922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Deformation-absorbing leadframe for semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/599778 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3973 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455922.pdf [firstpage_image] =>[orig_patent_app_number] => 09599778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599778
Deformation-absorbing leadframe for semiconductor devices Jun 20, 2000 Issued
Array ( [id] => 1476314 [patent_doc_number] => 06388293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Nonvolatile memory cell, operating method of the same and nonvolatile memory array' [patent_app_type] => B1 [patent_app_number] => 09/595059 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 17031 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388293.pdf [firstpage_image] =>[orig_patent_app_number] => 09595059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595059
Nonvolatile memory cell, operating method of the same and nonvolatile memory array Jun 15, 2000 Issued
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