Marcos D. Pizarro Crespo

Array ( [id] => 4404407 [patent_doc_number] => 06271063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of making an SRAM cell and structure' [patent_app_type] => 1 [patent_app_number] => 9/593334 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4785 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271063.pdf [firstpage_image] =>[orig_patent_app_number] => 593334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1394956 [patent_doc_number] => 06548825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Semiconductor device including barrier layer having dispersed particles' [patent_app_type] => B1 [patent_app_number] => 09/587268 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 72 [patent_no_of_words] => 45160 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548825.pdf [firstpage_image] =>[orig_patent_app_number] => 09587268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1409619 [patent_doc_number] => 06534792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Microelectronic device structure with metallic interlayer between substrate and die' [patent_app_type] => B1 [patent_app_number] => 09/573249 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3274 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534792.pdf [firstpage_image] =>[orig_patent_app_number] => 09573249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561133 [patent_doc_number] => 06362061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method to differentiate source/drain doping by using oxide slivers' [patent_app_type] => B1 [patent_app_number] => 09/566659 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 1119 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362061.pdf [firstpage_image] =>[orig_patent_app_number] => 09566659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1231374 [patent_doc_number] => 06693021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'GaN single crystal substrate and method of making the same' [patent_app_type] => B1 [patent_app_number] => 09/560818 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 19344 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693021.pdf [firstpage_image] =>[orig_patent_app_number] => 09560818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1328081 [patent_doc_number] => 06603168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method' [patent_app_type] => B1 [patent_app_number] => 09/553868 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3236 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603168.pdf [firstpage_image] =>[orig_patent_app_number] => 09553868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424142 [patent_doc_number] => 06507063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Poly-poly/MOS capacitor having a gate encapsulating first electrode layer' [patent_app_type] => B2 [patent_app_number] => 09/551168 [patent_app_country] => US [patent_app_date] => 2000-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3509 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507063.pdf [firstpage_image] =>[orig_patent_app_number] => 09551168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6427144 [patent_doc_number] => 20020175349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Semiconductor Memory Device Having Auxiliary Conduction Region Of Deduced Area' [patent_app_type] => new [patent_app_number] => 09/548888 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175349.pdf [firstpage_image] =>[orig_patent_app_number] => 09548888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1461469 [patent_doc_number] => 06392281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Ferromagnetic tunnel junction device and method of forming the same' [patent_app_type] => B1 [patent_app_number] => 09/536698 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 137 [patent_no_of_words] => 41211 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392281.pdf [firstpage_image] =>[orig_patent_app_number] => 09536698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1554628 [patent_doc_number] => 06348706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method to form etch and/or CMP stop layers' [patent_app_type] => B1 [patent_app_number] => 09/531680 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4004 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348706.pdf [firstpage_image] =>[orig_patent_app_number] => 09531680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1492557 [patent_doc_number] => 06402792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Electric double layer capacitor and process for its production' [patent_app_type] => B1 [patent_app_number] => 09/515318 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/402/06402792.pdf [firstpage_image] =>[orig_patent_app_number] => 09515318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 770156 [patent_doc_number] => 07005695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-28 [patent_title] => 'Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region' [patent_app_type] => utility [patent_app_number] => 09/512149 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3249 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005695.pdf [firstpage_image] =>[orig_patent_app_number] => 09512149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561820 [patent_doc_number] => 06437424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Non-volatile semiconductor memory device with barrier and insulating films' [patent_app_type] => B1 [patent_app_number] => 09/505980 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6063 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437424.pdf [firstpage_image] =>[orig_patent_app_number] => 09505980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459918 [patent_doc_number] => 06426545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Integrated circuit structures and methods employing a low modulus high elongation photodielectric' [patent_app_type] => B1 [patent_app_number] => 09/502078 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6902 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426545.pdf [firstpage_image] =>[orig_patent_app_number] => 09502078 [rel_patent_id] =>[rel_patent_doc_number] =>)