Search

Marcos D. Pizarro Crespo

Examiner (ID: 8349, Phone: (571)272-1716 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
1073
Issued Applications
704
Pending Applications
106
Abandoned Applications
293

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1435884 [patent_doc_number] => 06355527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method to increase coupling ratio of source to floating gate in split-gate flash' [patent_app_type] => B1 [patent_app_number] => 09/314588 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3982 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355527.pdf [firstpage_image] =>[orig_patent_app_number] => 09314588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314588
Method to increase coupling ratio of source to floating gate in split-gate flash May 18, 1999 Issued
Array ( [id] => 4387283 [patent_doc_number] => 06294812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'High density flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/306119 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2173 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294812.pdf [firstpage_image] =>[orig_patent_app_number] => 306119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306119
High density flash memory cell May 5, 1999 Issued
Array ( [id] => 1578195 [patent_doc_number] => 06448154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method for producing wafers with rounded corners in the notches used for alignment in the fabrication of semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/289499 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2090 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448154.pdf [firstpage_image] =>[orig_patent_app_number] => 09289499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289499
Method for producing wafers with rounded corners in the notches used for alignment in the fabrication of semiconductor devices Apr 8, 1999 Issued
Array ( [id] => 4380504 [patent_doc_number] => 06277658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method for monitoring alignment mark shielding' [patent_app_type] => 1 [patent_app_number] => 9/282059 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277658.pdf [firstpage_image] =>[orig_patent_app_number] => 282059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282059
Method for monitoring alignment mark shielding Mar 28, 1999 Issued
Array ( [id] => 4401741 [patent_doc_number] => 06297564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Electronic devices employing adhesive interconnections including plated particles' [patent_app_type] => 1 [patent_app_number] => 9/276259 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5971 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297564.pdf [firstpage_image] =>[orig_patent_app_number] => 276259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276259
Electronic devices employing adhesive interconnections including plated particles Mar 24, 1999 Issued
Array ( [id] => 4355650 [patent_doc_number] => 06215180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Dual-sided heat dissipating structure for integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 9/270808 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2944 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215180.pdf [firstpage_image] =>[orig_patent_app_number] => 270808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270808
Dual-sided heat dissipating structure for integrated circuit package Mar 16, 1999 Issued
09/241609 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Feb 1, 1999 Abandoned
Array ( [id] => 5798595 [patent_doc_number] => 20020008301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'MONOLITHIC HIGH-Q INDUCTANCE DEVICE AND PROCESS FOR FABRICATING THE SAME' [patent_app_type] => new [patent_app_number] => 09/212319 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3272 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008301.pdf [firstpage_image] =>[orig_patent_app_number] => 09212319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212319
MONOLITHIC HIGH-Q INDUCTANCE DEVICE AND PROCESS FOR FABRICATING THE SAME Dec 14, 1998 Abandoned
Array ( [id] => 1397645 [patent_doc_number] => 06531416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method for heat treatment of silicon wafer and silicon wafer heat-treated by the method' [patent_app_type] => B1 [patent_app_number] => 09/178179 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5119 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531416.pdf [firstpage_image] =>[orig_patent_app_number] => 09178179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178179
Method for heat treatment of silicon wafer and silicon wafer heat-treated by the method Oct 22, 1998 Issued
Array ( [id] => 1435900 [patent_doc_number] => 06355543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Laser annealing for forming shallow source/drain extension for MOS transistor' [patent_app_type] => B1 [patent_app_number] => 09/162919 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2334 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355543.pdf [firstpage_image] =>[orig_patent_app_number] => 09162919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162919
Laser annealing for forming shallow source/drain extension for MOS transistor Sep 28, 1998 Issued
Array ( [id] => 1545272 [patent_doc_number] => 06444549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-03 [patent_title] => 'Thermal processing of semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 09/144938 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3465 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444549.pdf [firstpage_image] =>[orig_patent_app_number] => 09144938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144938
Thermal processing of semiconductor devices Aug 31, 1998 Issued
Array ( [id] => 4405662 [patent_doc_number] => 06232205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/119778 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3873 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232205.pdf [firstpage_image] =>[orig_patent_app_number] => 119778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/119778
Method for producing a semiconductor device Jul 20, 1998 Issued
Array ( [id] => 1374881 [patent_doc_number] => 06566737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Passivation structure for an integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/115418 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3447 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566737.pdf [firstpage_image] =>[orig_patent_app_number] => 09115418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115418
Passivation structure for an integrated circuit Jul 13, 1998 Issued
Array ( [id] => 1507400 [patent_doc_number] => 06440828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Process of fabricating semiconductor device having low-resistive contact without high temperature heat treatment' [patent_app_type] => B1 [patent_app_number] => 08/866330 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 8575 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440828.pdf [firstpage_image] =>[orig_patent_app_number] => 08866330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866330
Process of fabricating semiconductor device having low-resistive contact without high temperature heat treatment May 29, 1997 Issued
Array ( [id] => 6091979 [patent_doc_number] => 20020050606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'SEMI-MONOLITHIC MEMORY WITH HIGH-DENSITY CELL CONFIGURATIONS' [patent_app_type] => new [patent_app_number] => 08/562750 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 21165 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20020050606.pdf [firstpage_image] =>[orig_patent_app_number] => 08562750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562750
SEMI-MONOLITHIC MEMORY WITH HIGH-DENSITY CELL CONFIGURATIONS Nov 26, 1995 Abandoned
08/339839 INTEGRATED CIRCUIT CAPACITORS UTILIZING LOW CURIE POINT FERROELECTRICS Nov 14, 1994 Abandoned
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