| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_title] => 'Method to increase coupling ratio of source to floating gate in split-gate flash'
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[patent_app_number] => 09/314588
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Array
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[patent_doc_number] => 06294812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'High density flash memory cell'
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[patent_app_number] => 9/306119
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[patent_app_date] => 1999-05-06
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[firstpage_image] =>[orig_patent_app_number] => 306119
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/306119 | High density flash memory cell | May 5, 1999 | Issued |
Array
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[id] => 1578195
[patent_doc_number] => 06448154
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Method for producing wafers with rounded corners in the notches used for alignment in the fabrication of semiconductor devices'
[patent_app_type] => B1
[patent_app_number] => 09/289499
[patent_app_country] => US
[patent_app_date] => 1999-04-09
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[firstpage_image] =>[orig_patent_app_number] => 09289499
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Array
(
[id] => 4380504
[patent_doc_number] => 06277658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method for monitoring alignment mark shielding'
[patent_app_type] => 1
[patent_app_number] => 9/282059
[patent_app_country] => US
[patent_app_date] => 1999-03-29
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 282059
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Array
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[id] => 4401741
[patent_doc_number] => 06297564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Electronic devices employing adhesive interconnections including plated particles'
[patent_app_type] => 1
[patent_app_number] => 9/276259
[patent_app_country] => US
[patent_app_date] => 1999-03-25
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[firstpage_image] =>[orig_patent_app_number] => 276259
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/276259 | Electronic devices employing adhesive interconnections including plated particles | Mar 24, 1999 | Issued |
Array
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[id] => 4355650
[patent_doc_number] => 06215180
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[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Dual-sided heat dissipating structure for integrated circuit package'
[patent_app_type] => 1
[patent_app_number] => 9/270808
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[patent_app_date] => 1999-03-17
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[firstpage_image] =>[orig_patent_app_number] => 270808
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270808 | Dual-sided heat dissipating structure for integrated circuit package | Mar 16, 1999 | Issued |
| 09/241609 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Feb 1, 1999 | Abandoned |
Array
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[id] => 5798595
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[patent_app_type] => new
[patent_app_number] => 09/212319
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[firstpage_image] =>[orig_patent_app_number] => 09212319
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212319 | MONOLITHIC HIGH-Q INDUCTANCE DEVICE AND PROCESS FOR FABRICATING THE SAME | Dec 14, 1998 | Abandoned |
Array
(
[id] => 1397645
[patent_doc_number] => 06531416
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Method for heat treatment of silicon wafer and silicon wafer heat-treated by the method'
[patent_app_type] => B1
[patent_app_number] => 09/178179
[patent_app_country] => US
[patent_app_date] => 1998-10-23
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[pdf_file] => patents/06/531/06531416.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178179 | Method for heat treatment of silicon wafer and silicon wafer heat-treated by the method | Oct 22, 1998 | Issued |
Array
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[id] => 1435900
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[patent_issue_date] => 2002-03-12
[patent_title] => 'Laser annealing for forming shallow source/drain extension for MOS transistor'
[patent_app_type] => B1
[patent_app_number] => 09/162919
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162919 | Laser annealing for forming shallow source/drain extension for MOS transistor | Sep 28, 1998 | Issued |
Array
(
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-03
[patent_title] => 'Thermal processing of semiconductor devices'
[patent_app_type] => B2
[patent_app_number] => 09/144938
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[firstpage_image] =>[orig_patent_app_number] => 09144938
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144938 | Thermal processing of semiconductor devices | Aug 31, 1998 | Issued |
Array
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[firstpage_image] =>[orig_patent_app_number] => 119778
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/119778 | Method for producing a semiconductor device | Jul 20, 1998 | Issued |
Array
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Array
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Array
(
[id] => 6091979
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[patent_app_type] => new
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[patent_app_date] => 1995-11-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/562750 | SEMI-MONOLITHIC MEMORY WITH HIGH-DENSITY CELL CONFIGURATIONS | Nov 26, 1995 | Abandoned |
| 08/339839 | INTEGRATED CIRCUIT CAPACITORS UTILIZING LOW CURIE POINT FERROELECTRICS | Nov 14, 1994 | Abandoned |