Search

Marcus A Jackson

Examiner (ID: 8879)

Most Active Art Unit
2916
Art Unit(s)
2913, 2900, 2901, 2911, 2916
Total Applications
11214
Issued Applications
11154
Pending Applications
1
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8816584 [patent_doc_number] => 20130117629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'BELIEF PROPAGATION PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/521505 [patent_app_country] => US [patent_app_date] => 2011-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14693 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13521505 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/521505
Belief propagation processor Jan 10, 2011 Issued
Array ( [id] => 6147293 [patent_doc_number] => 20110131370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL' [patent_app_type] => utility [patent_app_number] => 12/977395 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12093 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131370.pdf [firstpage_image] =>[orig_patent_app_number] => 12977395 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/977395
Disabling outbound drivers for a last memory buffer on a memory channel Dec 22, 2010 Issued
Array ( [id] => 6040703 [patent_doc_number] => 20110093752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'Method and Apparatus for Synthesis of Augmented Multimode Compactors' [patent_app_type] => utility [patent_app_number] => 12/976042 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093752.pdf [firstpage_image] =>[orig_patent_app_number] => 12976042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/976042
Method and apparatus for synthesis of augmented multimode compactors Dec 21, 2010 Issued
Array ( [id] => 7537700 [patent_doc_number] => 08051343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Method of testing a memory module and hub of the memory module' [patent_app_type] => utility [patent_app_number] => 12/926043 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 15 [patent_no_of_words] => 7842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051343.pdf [firstpage_image] =>[orig_patent_app_number] => 12926043 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926043
Method of testing a memory module and hub of the memory module Oct 21, 2010 Issued
Array ( [id] => 7517930 [patent_doc_number] => 08042012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Systems and devices including memory with built-in self test and methods of making and using the same' [patent_app_type] => utility [patent_app_number] => 12/903936 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11299 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/042/08042012.pdf [firstpage_image] =>[orig_patent_app_number] => 12903936 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903936
Systems and devices including memory with built-in self test and methods of making and using the same Oct 12, 2010 Issued
Array ( [id] => 8109483 [patent_doc_number] => 08156396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-10 [patent_title] => 'Method and system for correcting timing errors in high data rate automated test equipment' [patent_app_type] => utility [patent_app_number] => 12/898621 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6468 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156396.pdf [firstpage_image] =>[orig_patent_app_number] => 12898621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/898621
Method and system for correcting timing errors in high data rate automated test equipment Oct 4, 2010 Issued
Array ( [id] => 6644276 [patent_doc_number] => 20100313080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'CAN SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/846404 [patent_app_country] => US [patent_app_date] => 2010-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11200 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313080.pdf [firstpage_image] =>[orig_patent_app_number] => 12846404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/846404
CAN system Jul 28, 2010 Issued
Array ( [id] => 6191987 [patent_doc_number] => 20110023741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'FUSE INFORMATION DETECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/843887 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4670 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20110023741.pdf [firstpage_image] =>[orig_patent_app_number] => 12843887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843887
FUSE INFORMATION DETECTION CIRCUIT Jul 26, 2010 Abandoned
Array ( [id] => 8242555 [patent_doc_number] => 20120151281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'APPARATUSES AND METHODS FOR IDENTIFICATION OF EXTERNAL INFLUENCES ON AT LEAST ONE PROCESSING UNIT OF AN EMBEDDED SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/391164 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/391164
APPARATUSES AND METHODS FOR IDENTIFICATION OF EXTERNAL INFLUENCES ON AT LEAST ONE PROCESSING UNIT OF AN EMBEDDED SYSTEM Jul 15, 2010 Abandoned
Array ( [id] => 6463399 [patent_doc_number] => 20100281315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'MEMORY CHANNEL WITH BIT LANE FAIL-OVER' [patent_app_type] => utility [patent_app_number] => 12/836953 [patent_app_country] => US [patent_app_date] => 2010-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281315.pdf [firstpage_image] =>[orig_patent_app_number] => 12836953 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/836953
Memory channel with bit lane fail-over Jul 14, 2010 Issued
Array ( [id] => 9062930 [patent_doc_number] => 08549384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Method and apparatus for determining, based on an error correction code, one or more locations to store data in a flash memory' [patent_app_type] => utility [patent_app_number] => 12/822664 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2666 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822664
Method and apparatus for determining, based on an error correction code, one or more locations to store data in a flash memory Jun 23, 2010 Issued
Array ( [id] => 9062925 [patent_doc_number] => 08549378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'RAIM system using decoding of virtual ECC' [patent_app_type] => utility [patent_app_number] => 12/822469 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13930 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822469
RAIM system using decoding of virtual ECC Jun 23, 2010 Issued
Array ( [id] => 7671652 [patent_doc_number] => 20110320921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/822498 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7509 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822498
Failing bus lane detection using syndrome analysis Jun 23, 2010 Issued
Array ( [id] => 7671597 [patent_doc_number] => 20110320866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'DYNAMIC PIPELINE CACHE ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/822437 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822437
Dynamic pipeline cache error correction Jun 23, 2010 Issued
Array ( [id] => 8899536 [patent_doc_number] => 08479070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Integrated circuit arrangement for test inputs' [patent_app_type] => utility [patent_app_number] => 12/822287 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822287
Integrated circuit arrangement for test inputs Jun 23, 2010 Issued
Array ( [id] => 8899547 [patent_doc_number] => 08479080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Adaptive over-provisioning in memory systems' [patent_app_type] => utility [patent_app_number] => 12/822207 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 11362 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822207 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822207
Adaptive over-provisioning in memory systems Jun 23, 2010 Issued
Array ( [id] => 8899546 [patent_doc_number] => 08479081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method for visually confirming a relationship between an edited packet and serial data' [patent_app_type] => utility [patent_app_number] => 12/822822 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3141 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822822
Method for visually confirming a relationship between an edited packet and serial data Jun 23, 2010 Issued
Array ( [id] => 8873033 [patent_doc_number] => 08468421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Memory system for error checking fetch and store data' [patent_app_type] => utility [patent_app_number] => 12/821917 [patent_app_country] => US [patent_app_date] => 2010-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3122 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12821917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/821917
Memory system for error checking fetch and store data Jun 22, 2010 Issued
Array ( [id] => 6365050 [patent_doc_number] => 20100251040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/815382 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 20295 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251040.pdf [firstpage_image] =>[orig_patent_app_number] => 12815382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/815382
Method and apparatus for evaluating and optimizing a signaling system Jun 13, 2010 Issued
Array ( [id] => 4447592 [patent_doc_number] => 07930604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Apparatus and method for testing and debugging an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/778225 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8695 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930604.pdf [firstpage_image] =>[orig_patent_app_number] => 12778225 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778225
Apparatus and method for testing and debugging an integrated circuit May 11, 2010 Issued
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