Search

Marcus A Jackson

Examiner (ID: 8879)

Most Active Art Unit
2916
Art Unit(s)
2913, 2900, 2901, 2911, 2916
Total Applications
11214
Issued Applications
11154
Pending Applications
1
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8985224 [patent_doc_number] => 08516354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method for reducing uncorrectable errors of a memory device regarding error correction code, and associated memory device and controller thereof' [patent_app_type] => utility [patent_app_number] => 12/774736 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5348 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774736 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774736
Method for reducing uncorrectable errors of a memory device regarding error correction code, and associated memory device and controller thereof May 5, 2010 Issued
Array ( [id] => 8861569 [patent_doc_number] => 08464123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Matrix structure for block encoding' [patent_app_type] => utility [patent_app_number] => 12/774746 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8087 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774746
Matrix structure for block encoding May 5, 2010 Issued
Array ( [id] => 6020564 [patent_doc_number] => 20110225475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR CHECKING AND CORRECTION FOR MEMORIES AND BUSES IN SYSTEM-ON-CHIPS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES' [patent_app_type] => utility [patent_app_number] => 12/774861 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17072 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225475.pdf [firstpage_image] =>[orig_patent_app_number] => 12774861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774861
Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes May 5, 2010 Issued
Array ( [id] => 8552302 [patent_doc_number] => 08327201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Parallel testing of an integrated circuit that includes multiple dies' [patent_app_type] => utility [patent_app_number] => 12/774668 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774668
Parallel testing of an integrated circuit that includes multiple dies May 4, 2010 Issued
Array ( [id] => 8667604 [patent_doc_number] => 08381077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Systems and methods for implementing error correction in relation to a flash memory' [patent_app_type] => utility [patent_app_number] => 12/774077 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5791 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774077
Systems and methods for implementing error correction in relation to a flash memory May 4, 2010 Issued
Array ( [id] => 6363719 [patent_doc_number] => 20100332932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/774002 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6903 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332932.pdf [firstpage_image] =>[orig_patent_app_number] => 12774002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774002
TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE May 4, 2010 Abandoned
Array ( [id] => 6272945 [patent_doc_number] => 20100299579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration' [patent_app_type] => utility [patent_app_number] => 12/774092 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20100299579.pdf [firstpage_image] =>[orig_patent_app_number] => 12774092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774092
Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration May 4, 2010 Abandoned
Array ( [id] => 6534844 [patent_doc_number] => 20100287447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION' [patent_app_type] => utility [patent_app_number] => 12/773179 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4241 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287447.pdf [firstpage_image] =>[orig_patent_app_number] => 12773179 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773179
MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION May 3, 2010 Abandoned
Array ( [id] => 7563027 [patent_doc_number] => 20110276861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'DEVICE, SYSTEM AND METHOD OF DECODING WIRELESS TRANSMISSIONS' [patent_app_type] => utility [patent_app_number] => 12/773050 [patent_app_country] => US [patent_app_date] => 2010-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276861.pdf [firstpage_image] =>[orig_patent_app_number] => 12773050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/773050
Device, system and method of decoding wireless transmissions May 3, 2010 Issued
Array ( [id] => 6555862 [patent_doc_number] => 20100205490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'INPUT/OUTPUT COMPRESSION AND PIN REDUCTION IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/767020 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205490.pdf [firstpage_image] =>[orig_patent_app_number] => 12767020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767020
Input/output compression and pin reduction in an integrated circuit Apr 25, 2010 Issued
Array ( [id] => 4508652 [patent_doc_number] => 07958413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method and system for memory testing and test data reporting during memory testing' [patent_app_type] => utility [patent_app_number] => 12/766809 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 7460 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958413.pdf [firstpage_image] =>[orig_patent_app_number] => 12766809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766809
Method and system for memory testing and test data reporting during memory testing Apr 22, 2010 Issued
Array ( [id] => 8773887 [patent_doc_number] => 08427854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Utilization of memory refresh cycles for pattern matching' [patent_app_type] => utility [patent_app_number] => 12/760797 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5222 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12760797 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760797
Utilization of memory refresh cycles for pattern matching Apr 14, 2010 Issued
Array ( [id] => 8546450 [patent_doc_number] => 08321753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Optimization of packet buffer memory utilization' [patent_app_type] => utility [patent_app_number] => 12/759313 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 15193 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759313
Optimization of packet buffer memory utilization Apr 12, 2010 Issued
Array ( [id] => 8923994 [patent_doc_number] => 08489943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Protocol sequence generator' [patent_app_type] => utility [patent_app_number] => 12/751111 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7862 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751111
Protocol sequence generator Mar 30, 2010 Issued
Array ( [id] => 8558210 [patent_doc_number] => 08332695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Data storage device tester' [patent_app_type] => utility [patent_app_number] => 12/749279 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 5412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/749279
Data storage device tester Mar 28, 2010 Issued
Array ( [id] => 8460924 [patent_doc_number] => 08296608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 12/748807 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4095 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748807
Memory device Mar 28, 2010 Issued
Array ( [id] => 8763317 [patent_doc_number] => 08423856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method and apparatus for semi-persistent scheduling activation detection' [patent_app_type] => utility [patent_app_number] => 12/748023 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748023
Method and apparatus for semi-persistent scheduling activation detection Mar 25, 2010 Issued
Array ( [id] => 7493248 [patent_doc_number] => 20110239098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'Detecting Data Error' [patent_app_type] => utility [patent_app_number] => 12/732682 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5650 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239098.pdf [firstpage_image] =>[orig_patent_app_number] => 12732682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732682
Detecting Data Error Mar 25, 2010 Abandoned
Array ( [id] => 6365417 [patent_doc_number] => 20100251081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'APPARATUS AND METHOD FOR ARQ FEEDBACK POLLING IN WIRELESS COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/732625 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10067 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251081.pdf [firstpage_image] =>[orig_patent_app_number] => 12732625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732625
Apparatus and method for ARQ feedback polling in wireless communication system Mar 25, 2010 Issued
Array ( [id] => 8378350 [patent_doc_number] => 08261162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Decoding device, decoding method, and media data delivery system' [patent_app_type] => utility [patent_app_number] => 12/731856 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 13185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12731856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731856
Decoding device, decoding method, and media data delivery system Mar 24, 2010 Issued
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