Search

Marcus A Jackson

Examiner (ID: 8879)

Most Active Art Unit
2916
Art Unit(s)
2913, 2900, 2901, 2911, 2916
Total Applications
11214
Issued Applications
11154
Pending Applications
1
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9044242 [patent_doc_number] => 20130246880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/781361 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781361 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/781361
LDPC selective decoding scheduling using a cost function Feb 27, 2013 Issued
Array ( [id] => 9658774 [patent_doc_number] => 20140229778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'AT-SPEED SCAN TESTING OF INTERFACE FUNCTIONAL LOGIC OF AN EMBEDDED MEMORY OR OTHER CIRCUIT CORE' [patent_app_type] => utility [patent_app_number] => 13/767467 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767467
At-speed scan testing of interface functional logic of an embedded memory or other circuit core Feb 13, 2013 Issued
Array ( [id] => 9658772 [patent_doc_number] => 20140229777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'AUTORECOVERY AFTER MANUFACTURING/SYSTEM INTEGRATION' [patent_app_type] => utility [patent_app_number] => 13/767389 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2621 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13767389 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/767389
Autorecovery after manufacturing/system integration Feb 13, 2013 Issued
Array ( [id] => 9820990 [patent_doc_number] => 08930792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Systems and methods for distributed low density parity check decoding' [patent_app_type] => utility [patent_app_number] => 13/766891 [patent_app_country] => US [patent_app_date] => 2013-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7252 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766891
Systems and methods for distributed low density parity check decoding Feb 13, 2013 Issued
Array ( [id] => 9926397 [patent_doc_number] => 08984383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Methods for decoding, methods for retrieving, method for encoding, method of transmitting, corresponding devices, information storage means and computer program products' [patent_app_type] => utility [patent_app_number] => 13/766586 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7154 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766586 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766586
Methods for decoding, methods for retrieving, method for encoding, method of transmitting, corresponding devices, information storage means and computer program products Feb 12, 2013 Issued
Array ( [id] => 10873329 [patent_doc_number] => 08898550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Encoding of data for transmission' [patent_app_type] => utility [patent_app_number] => 13/765382 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8144 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765382
Encoding of data for transmission Feb 11, 2013 Issued
Array ( [id] => 10873328 [patent_doc_number] => 08898549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Statistical adaptive error correction for a flash memory' [patent_app_type] => utility [patent_app_number] => 13/765034 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765034
Statistical adaptive error correction for a flash memory Feb 11, 2013 Issued
Array ( [id] => 9853072 [patent_doc_number] => 08954820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Reduced complexity non-binary LDPC decoding algorithm' [patent_app_type] => utility [patent_app_number] => 13/764649 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 11238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764649 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764649
Reduced complexity non-binary LDPC decoding algorithm Feb 10, 2013 Issued
Array ( [id] => 9834552 [patent_doc_number] => 08943386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Generating soft read values which optimize dynamic range' [patent_app_type] => utility [patent_app_number] => 13/764515 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764515 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764515
Generating soft read values which optimize dynamic range Feb 10, 2013 Issued
Array ( [id] => 9486582 [patent_doc_number] => 08732544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Semiconductor memory device and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 13/757935 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6067 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757935 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757935
Semiconductor memory device and method of controlling the same Feb 3, 2013 Issued
Array ( [id] => 9829420 [patent_doc_number] => 08938659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'Low-density parity-check decoder disparity preprocessing' [patent_app_type] => utility [patent_app_number] => 13/753987 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753987 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753987
Low-density parity-check decoder disparity preprocessing Jan 29, 2013 Issued
Array ( [id] => 9224896 [patent_doc_number] => 20140019671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'Flash Memory Controllers and Error Detection Methods' [patent_app_type] => utility [patent_app_number] => 13/750459 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3140 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750459 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750459
Flash memory controllers and error detection methods Jan 24, 2013 Issued
Array ( [id] => 9116256 [patent_doc_number] => 08572448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Apparatus and method for testing and debugging an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/741496 [patent_app_country] => US [patent_app_date] => 2013-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8783 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741496 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/741496
Apparatus and method for testing and debugging an integrated circuit Jan 14, 2013 Issued
Array ( [id] => 9599200 [patent_doc_number] => 20140195881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'BOSE-CHAUDHURI-HOCQUENGHEM (BCH) DECODER' [patent_app_type] => utility [patent_app_number] => 13/735052 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735052
Bose-Chaudhuri-Hocquenghem (BCH) decoder Jan 6, 2013 Issued
Array ( [id] => 10847780 [patent_doc_number] => 08874980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Chip applied to serial transmission system and associated fail safe method' [patent_app_type] => utility [patent_app_number] => 13/735019 [patent_app_country] => US [patent_app_date] => 2013-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5240 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735019 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735019
Chip applied to serial transmission system and associated fail safe method Jan 5, 2013 Issued
Array ( [id] => 10895074 [patent_doc_number] => 08918705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'Error recovery by modifying soft information' [patent_app_type] => utility [patent_app_number] => 13/734108 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2939 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734108 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734108
Error recovery by modifying soft information Jan 3, 2013 Issued
Array ( [id] => 9599186 [patent_doc_number] => 20140195867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'MEMORY TESTING WITH SELECTIVE USE OF AN ERROR CORRECTION CODE DECODER' [patent_app_type] => utility [patent_app_number] => 13/734334 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734334
Memory testing with selective use of an error correction code decoder Jan 3, 2013 Issued
Array ( [id] => 9571748 [patent_doc_number] => 20140189461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'UNEQUAL ERROR PROTECTION SCHEME FOR HEADERIZED SUB DATA SETS' [patent_app_type] => utility [patent_app_number] => 13/733847 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13431 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733847 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733847
Unequal error protection scheme for headerized sub data sets Jan 2, 2013 Issued
Array ( [id] => 9571746 [patent_doc_number] => 20140189459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD AND SYSTEM FOR OPERATING A COMMUNICATION CIRCUIT CONFIGURABLE TO SUPPORT ONE OR MORE DATA RATES' [patent_app_type] => utility [patent_app_number] => 13/733798 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733798
Method and system for operating a communication circuit configurable to support one or more data rates Jan 2, 2013 Issued
Array ( [id] => 8906467 [patent_doc_number] => 20130173970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND BUILT-IN SELF-REPAIR' [patent_app_type] => utility [patent_app_number] => 13/732783 [patent_app_country] => US [patent_app_date] => 2013-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20791 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/732783
Memory device with background built-in self-testing and background built-in self-repair Jan 1, 2013 Issued
Menu