Marcus A Jackson

Array ( [id] => 9156862 [patent_doc_number] => 08589776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Translation between a first communication protocol and a second communication protocol' [patent_app_type] => utility [patent_app_number] => 13/150486 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5122 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8763302 [patent_doc_number] => 08423841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method and systems for memory testing and test data reporting during memory testing' [patent_app_type] => utility [patent_app_number] => 13/118739 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 7504 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9680596 [patent_doc_number] => 08819523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Adaptive controller for a configurable audio coding system' [patent_app_type] => utility [patent_app_number] => 13/111420 [patent_app_country] => US [patent_app_date] => 2011-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7090 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13111420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9029696 [patent_doc_number] => 08539293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Integrated circuit for compression mode scan test' [patent_app_type] => utility [patent_app_number] => 13/098749 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8455107 [patent_doc_number] => 20120266053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'SECURITY COMMUNICATION METHOD BETWEEN DEVICES' [patent_app_type] => utility [patent_app_number] => 13/098463 [patent_app_country] => US [patent_app_date] => 2011-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3081 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9242315 [patent_doc_number] => 08607121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Selective error detection and error correction for a memory interface' [patent_app_type] => utility [patent_app_number] => 13/097721 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220246 [patent_doc_number] => 08195992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Processor-memory unit for use in system-in-package and system-in-module devices' [patent_app_type] => utility [patent_app_number] => 13/093720 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195992.pdf [firstpage_image] =>[orig_patent_app_number] => 13093720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6171790 [patent_doc_number] => 20110197110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/090539 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6014 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20110197110.pdf [firstpage_image] =>[orig_patent_app_number] => 13090539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7557484 [patent_doc_number] => 08069394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Semiconductor memory device and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 13/090499 [patent_app_country] => US [patent_app_date] => 2011-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6012 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069394.pdf [firstpage_image] =>[orig_patent_app_number] => 13090499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8120229 [patent_doc_number] => 08161336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-17 [patent_title] => 'Apparatus and method for testing and debugging an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/089660 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8717 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161336.pdf [firstpage_image] =>[orig_patent_app_number] => 13089660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6171133 [patent_doc_number] => 20110196905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'STORING DATA TO MULTI-CHIP LOW-LATENCY RANDOM READ MEMORY DEVICE USING NON-ALIGNED STRIPING' [patent_app_type] => utility [patent_app_number] => 13/087710 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20110196905.pdf [firstpage_image] =>[orig_patent_app_number] => 13087710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6094149 [patent_doc_number] => 20110219278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Panel Driving Circuit That Generates Panel Test Pattern and Panel Test Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/085800 [patent_app_country] => US [patent_app_date] => 2011-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4559 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219278.pdf [firstpage_image] =>[orig_patent_app_number] => 13085800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8170822 [patent_doc_number] => 08176371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Embedded processor' [patent_app_type] => utility [patent_app_number] => 13/083975 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8788 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176371.pdf [firstpage_image] =>[orig_patent_app_number] => 13083975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5960856 [patent_doc_number] => 20110185243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'CONTROLLING TWO JTAG TAP CONTROLLERS WITH ONE SET OF JTAG PINS' [patent_app_type] => utility [patent_app_number] => 13/080270 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6110 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185243.pdf [firstpage_image] =>[orig_patent_app_number] => 13080270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8608661 [patent_doc_number] => 20130013974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'DATA ENCODING IN SOLID STATE STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/582768 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5920 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13582768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6147470 [patent_doc_number] => 20110131468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'ERROR DETECTION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/032393 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 24494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131468.pdf [firstpage_image] =>[orig_patent_app_number] => 13032393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8524900 [patent_doc_number] => 20120324308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'WIRELESS COMMUNICATION SYSTEM, COMMUNICATION DEVICE, PROGRAM, AND INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/580339 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20079 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9036309 [patent_doc_number] => 20130238947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'MEMORY DIAGNOSTIC APPARATUS AND MEMORY DIAGNOSTIC METHOD AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/885779 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2460 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13885779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8158343 [patent_doc_number] => 08171353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'System and method for initializing a memory system, and memory device and processor-based system using same' [patent_app_type] => utility [patent_app_number] => 13/023271 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9459 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171353.pdf [firstpage_image] =>[orig_patent_app_number] => 13023271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787109 [patent_doc_number] => 08433964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Test apparatus and test method' [patent_app_type] => utility [patent_app_number] => 13/015484 [patent_app_country] => US [patent_app_date] => 2011-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4654 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13015484 [rel_patent_id] =>[rel_patent_doc_number] =>)