
Marcus E. Windrich
Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )
| Most Active Art Unit | 3646 |
| Art Unit(s) | 3646, 3619 |
| Total Applications | 906 |
| Issued Applications | 670 |
| Pending Applications | 85 |
| Abandoned Applications | 168 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16966190
[patent_doc_number] => 20210217689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-15
[patent_title] => ENCAPSULATED VERTICAL INTERCONNECTS FOR HIGH-SPEED APPLICATIONS AND METHODS OF ASSEMBLING SAME
[patent_app_type] => utility
[patent_app_number] => 17/218384
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7266
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218384
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/218384 | Encapsulated vertical interconnects for high-speed applications and methods of assembling same | Mar 30, 2021 | Issued |
Array
(
[id] => 19704978
[patent_doc_number] => 12199025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Interposer structure containing embedded silicon-less link chiplet
[patent_app_type] => utility
[patent_app_number] => 17/207914
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 7367
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 381
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207914
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/207914 | Interposer structure containing embedded silicon-less link chiplet | Mar 21, 2021 | Issued |
Array
(
[id] => 16949524
[patent_doc_number] => 20210208215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => MAGNETIC SENSOR
[patent_app_type] => utility
[patent_app_number] => 17/205222
[patent_app_country] => US
[patent_app_date] => 2021-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4944
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205222
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/205222 | Magnetic sensor | Mar 17, 2021 | Issued |
Array
(
[id] => 17886526
[patent_doc_number] => 20220302004
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/205967
[patent_app_country] => US
[patent_app_date] => 2021-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7167
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205967
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/205967 | Semiconductor device package | Mar 17, 2021 | Issued |
Array
(
[id] => 17878524
[patent_doc_number] => 11450547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Method for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/202055
[patent_app_country] => US
[patent_app_date] => 2021-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 32
[patent_no_of_words] => 8565
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202055
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202055 | Method for manufacturing semiconductor device | Mar 14, 2021 | Issued |
Array
(
[id] => 17863025
[patent_doc_number] => 11444187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-13
[patent_title] => Insulated gate bipolar transistor and diode
[patent_app_type] => utility
[patent_app_number] => 17/200209
[patent_app_country] => US
[patent_app_date] => 2021-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 8233
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200209
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/200209 | Insulated gate bipolar transistor and diode | Mar 11, 2021 | Issued |
Array
(
[id] => 17855335
[patent_doc_number] => 20220285378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/249552
[patent_app_country] => US
[patent_app_date] => 2021-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15999
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249552
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/249552 | Microelectronic devices, memory devices, and electronic systems | Mar 3, 2021 | Issued |
Array
(
[id] => 17389454
[patent_doc_number] => 20220037306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/190689
[patent_app_country] => US
[patent_app_date] => 2021-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190689
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/190689 | Semiconductor package | Mar 2, 2021 | Issued |
Array
(
[id] => 17764779
[patent_doc_number] => 20220238392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => Method for detecting optimal production conditions of wafers
[patent_app_type] => utility
[patent_app_number] => 17/189214
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2835
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189214
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/189214 | Method for detecting optimal production conditions of wafers | Feb 28, 2021 | Abandoned |
Array
(
[id] => 17840761
[patent_doc_number] => 20220278067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => PACKAGE STRUCTURE INCLUDING IPD AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/185970
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12477
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185970
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/185970 | Package structure including IPD and method of forming the same | Feb 25, 2021 | Issued |
Array
(
[id] => 17840730
[patent_doc_number] => 20220278036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME
[patent_app_type] => utility
[patent_app_number] => 17/187138
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8275
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187138
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187138 | Semiconductor package and method of forming same | Feb 25, 2021 | Issued |
Array
(
[id] => 17402917
[patent_doc_number] => 20220045008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-10
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/183562
[patent_app_country] => US
[patent_app_date] => 2021-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9846
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183562
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/183562 | Semiconductor package and method of fabricating the same | Feb 23, 2021 | Issued |
Array
(
[id] => 18415993
[patent_doc_number] => 11670539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Method of making a semiconductor arrangement
[patent_app_type] => utility
[patent_app_number] => 17/181464
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 7984
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181464
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/181464 | Method of making a semiconductor arrangement | Feb 21, 2021 | Issued |
Array
(
[id] => 18935476
[patent_doc_number] => 11887919
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-30
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/181116
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10596
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181116
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/181116 | Semiconductor package | Feb 21, 2021 | Issued |
Array
(
[id] => 18464363
[patent_doc_number] => 11688657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Semiconductor devices and methods of manufacturing semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/172210
[patent_app_country] => US
[patent_app_date] => 2021-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 5563
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172210
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/172210 | Semiconductor devices and methods of manufacturing semiconductor devices | Feb 9, 2021 | Issued |
Array
(
[id] => 18219545
[patent_doc_number] => 11594494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => High density interconnection using fanout interposer chiplet
[patent_app_type] => utility
[patent_app_number] => 17/166795
[patent_app_country] => US
[patent_app_date] => 2021-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 5442
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166795
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/166795 | High density interconnection using fanout interposer chiplet | Feb 2, 2021 | Issued |
Array
(
[id] => 18073689
[patent_doc_number] => 11532528
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Electronic package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/160720
[patent_app_country] => US
[patent_app_date] => 2021-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3673
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160720
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/160720 | Electronic package and manufacturing method thereof | Jan 27, 2021 | Issued |
Array
(
[id] => 17758132
[patent_doc_number] => 11398431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Through-silicon via for high-speed interconnects
[patent_app_type] => utility
[patent_app_number] => 17/158041
[patent_app_country] => US
[patent_app_date] => 2021-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 6330
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158041
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/158041 | Through-silicon via for high-speed interconnects | Jan 25, 2021 | Issued |
Array
(
[id] => 17738080
[patent_doc_number] => 20220223542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/148572
[patent_app_country] => US
[patent_app_date] => 2021-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148572 | Semiconductor device and manufacturing method thereof | Jan 13, 2021 | Issued |
Array
(
[id] => 18137273
[patent_doc_number] => 11562962
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Package comprising a substrate and interconnect device configured for diagonal routing
[patent_app_type] => utility
[patent_app_number] => 17/148367
[patent_app_country] => US
[patent_app_date] => 2021-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 14241
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148367
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/148367 | Package comprising a substrate and interconnect device configured for diagonal routing | Jan 12, 2021 | Issued |