
Marcus E. Windrich
Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )
| Most Active Art Unit | 3646 |
| Art Unit(s) | 3646, 3619 |
| Total Applications | 906 |
| Issued Applications | 670 |
| Pending Applications | 85 |
| Abandoned Applications | 168 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16560497
[patent_doc_number] => 20210005646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => PHOTODETECTOR
[patent_app_type] => utility
[patent_app_number] => 17/026864
[patent_app_country] => US
[patent_app_date] => 2020-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026864
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/026864 | Photodetector | Sep 20, 2020 | Issued |
Array
(
[id] => 16711057
[patent_doc_number] => 20210078204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => CUTTING BLADE AND MANUFACTURING METHOD OF CUTTING BLADE
[patent_app_type] => utility
[patent_app_number] => 17/016713
[patent_app_country] => US
[patent_app_date] => 2020-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6243
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016713
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/016713 | CUTTING BLADE AND MANUFACTURING METHOD OF CUTTING BLADE | Sep 9, 2020 | Abandoned |
Array
(
[id] => 16889129
[patent_doc_number] => 20210175326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => Integrated Circuit Package for Isolation Dies
[patent_app_type] => utility
[patent_app_number] => 17/017642
[patent_app_country] => US
[patent_app_date] => 2020-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3561
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017642
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/017642 | Integrated circuit package for isolation dies | Sep 9, 2020 | Issued |
Array
(
[id] => 17716553
[patent_doc_number] => 11380551
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Method of processing target object
[patent_app_type] => utility
[patent_app_number] => 16/997125
[patent_app_country] => US
[patent_app_date] => 2020-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 11942
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997125
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/997125 | Method of processing target object | Aug 18, 2020 | Issued |
Array
(
[id] => 16487737
[patent_doc_number] => 20200381346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => Packages with Si-Substrate-Free Interposer and Method Forming Same
[patent_app_type] => utility
[patent_app_number] => 16/995014
[patent_app_country] => US
[patent_app_date] => 2020-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8566
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995014
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/995014 | Packages with Si-substrate-free interposer and method forming same | Aug 16, 2020 | Issued |
Array
(
[id] => 17417084
[patent_doc_number] => 20220051988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => PACKAGES WITH LOCAL HIGH-DENSITY ROUTING REGION EMBEDDED WITHIN AN INSULATING LAYER
[patent_app_type] => utility
[patent_app_number] => 16/994398
[patent_app_country] => US
[patent_app_date] => 2020-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6565
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -55
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994398
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/994398 | Packages with local high-density routing region embedded within an insulating layer | Aug 13, 2020 | Issued |
Array
(
[id] => 17590934
[patent_doc_number] => 11329211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-10
[patent_title] => Current crowding in three-terminal superconducting devices and related methods
[patent_app_type] => utility
[patent_app_number] => 16/992458
[patent_app_country] => US
[patent_app_date] => 2020-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 9916
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992458
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/992458 | Current crowding in three-terminal superconducting devices and related methods | Aug 12, 2020 | Issued |
Array
(
[id] => 17901086
[patent_doc_number] => 20220310748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => DISPLAY SUBSTRATE AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/413063
[patent_app_country] => US
[patent_app_date] => 2020-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413063
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/413063 | Display substrate and display device | Aug 2, 2020 | Issued |
Array
(
[id] => 17833654
[patent_doc_number] => 20220270958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-25
[patent_title] => ELECTRONIC ELEMENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, ELECTRONIC MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC ELEMENT MOUNTING SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/630194
[patent_app_country] => US
[patent_app_date] => 2020-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17630194
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/630194 | ELECTRONIC ELEMENT MOUNTING SUBSTRATE, ELECTRONIC DEVICE, ELECTRONIC MODULE, AND METHOD FOR MANUFACTURING ELECTRONIC ELEMENT MOUNTING SUBSTRATE | Jul 28, 2020 | Abandoned |
Array
(
[id] => 17787717
[patent_doc_number] => 11410851
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
[patent_app_type] => utility
[patent_app_number] => 16/936950
[patent_app_country] => US
[patent_app_date] => 2020-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8464
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936950
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/936950 | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures | Jul 22, 2020 | Issued |
Array
(
[id] => 17373721
[patent_doc_number] => 20220028773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/934024
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6225
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934024
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/934024 | Package structure and fabricating method thereof | Jul 20, 2020 | Issued |
Array
(
[id] => 16425012
[patent_doc_number] => 20200350210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE IN DUAL STRESS LINER PROCESS FLOW
[patent_app_type] => utility
[patent_app_number] => 16/931818
[patent_app_country] => US
[patent_app_date] => 2020-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1898
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931818
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931818 | Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow | Jul 16, 2020 | Issued |
Array
(
[id] => 16601482
[patent_doc_number] => 20210028013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => Surface Roughness for Flowable CVD Film
[patent_app_type] => utility
[patent_app_number] => 16/929357
[patent_app_country] => US
[patent_app_date] => 2020-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4311
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929357
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/929357 | Surface roughness for flowable CVD film | Jul 14, 2020 | Issued |
Array
(
[id] => 17825711
[patent_doc_number] => 11430665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-30
[patent_title] => Methods of manufacturing semiconductor devices and apparatuses for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/928548
[patent_app_country] => US
[patent_app_date] => 2020-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 10724
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928548
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/928548 | Methods of manufacturing semiconductor devices and apparatuses for manufacturing the same | Jul 13, 2020 | Issued |
Array
(
[id] => 16402238
[patent_doc_number] => 20200343096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-29
[patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/928001
[patent_app_country] => US
[patent_app_date] => 2020-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928001
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/928001 | Package structure and method of manufacturing the same | Jul 13, 2020 | Issued |
Array
(
[id] => 17318965
[patent_doc_number] => 20210408015
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => PACKAGE EMBEDDED PROGRAMMABLE RESISTOR FOR VOLTAGE DROOP MITIGATION
[patent_app_type] => utility
[patent_app_number] => 16/917212
[patent_app_country] => US
[patent_app_date] => 2020-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8776
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917212
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/917212 | Package embedded programmable resistor for voltage droop mitigation | Jun 29, 2020 | Issued |
Array
(
[id] => 16379330
[patent_doc_number] => 20200328173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/914478
[patent_app_country] => US
[patent_app_date] => 2020-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9757
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914478
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914478 | Integrated fan-out package and manufacturing method thereof | Jun 28, 2020 | Issued |
Array
(
[id] => 16364491
[patent_doc_number] => 20200321242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-08
[patent_title] => METHOD OF SEPARATING A FILM FROM A BRITTLE MATERIAL
[patent_app_type] => utility
[patent_app_number] => 16/904516
[patent_app_country] => US
[patent_app_date] => 2020-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904516
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/904516 | METHOD OF SEPARATING A FILM FROM A BRITTLE MATERIAL | Jun 16, 2020 | Abandoned |
Array
(
[id] => 16348227
[patent_doc_number] => 20200312878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/903070
[patent_app_country] => US
[patent_app_date] => 2020-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11021
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903070
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/903070 | Vertical semiconductor devices and methods of manufacturing the same | Jun 15, 2020 | Issued |
Array
(
[id] => 18381973
[patent_doc_number] => 20230157064
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => OLED DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/963498
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4235
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16963498
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/963498 | OLED DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE | Jun 14, 2020 | Abandoned |