Search

Marcus E. Windrich

Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3646, 3619
Total Applications
906
Issued Applications
670
Pending Applications
85
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17574101 [patent_doc_number] => 11322375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Light irradiation type heat treatment method and heat treatment apparatus [patent_app_type] => utility [patent_app_number] => 16/727129 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10525 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727129
Light irradiation type heat treatment method and heat treatment apparatus Dec 25, 2019 Issued
Array ( [id] => 17745679 [patent_doc_number] => 11393761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Circuit board and its manufacturing method [patent_app_type] => utility [patent_app_number] => 16/724232 [patent_app_country] => US [patent_app_date] => 2019-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 5473 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724232 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724232
Circuit board and its manufacturing method Dec 20, 2019 Issued
Array ( [id] => 16479615 [patent_doc_number] => 10854569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Package structure, semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/714824 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714824
Package structure, semiconductor device and method of fabricating the same Dec 15, 2019 Issued
Array ( [id] => 16249466 [patent_doc_number] => 10748841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Packages with Si-substrate-free interposer and method forming same [patent_app_type] => utility [patent_app_number] => 16/680809 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 8535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680809
Packages with Si-substrate-free interposer and method forming same Nov 11, 2019 Issued
Array ( [id] => 19567893 [patent_doc_number] => 12142675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/616691 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 48 [patent_no_of_words] => 18044 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17616691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/616691
Semiconductor device and method of manufacturing the same Nov 10, 2019 Issued
Array ( [id] => 16464370 [patent_doc_number] => 10847735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Foldable display device having a supporter [patent_app_type] => utility [patent_app_number] => 16/676947 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8176 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676947
Foldable display device having a supporter Nov 6, 2019 Issued
Array ( [id] => 16233840 [patent_doc_number] => 10741403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures [patent_app_type] => utility [patent_app_number] => 16/674894 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8422 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674894 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674894
Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures Nov 4, 2019 Issued
Array ( [id] => 15532667 [patent_doc_number] => 20200058639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => HIGH SWITCHING FREQUENCY, LOW LOSS AND SMALL FORM FACTOR FULLY INTEGRATED POWER STAGE [patent_app_type] => utility [patent_app_number] => 16/663779 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663779
High switching frequency, low loss and small form factor fully integrated power stage Oct 24, 2019 Issued
Array ( [id] => 15532897 [patent_doc_number] => 20200058754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => GATE SPACER AND METHODS OF FORMING [patent_app_type] => utility [patent_app_number] => 16/663891 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663891
Gate spacer and method of forming Oct 24, 2019 Issued
Array ( [id] => 17417054 [patent_doc_number] => 20220051958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => METHOD FOR PRODUCING PACKAGE SUBSTRATE FOR MOUNTING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/413277 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413277
Method for producing package substrate for mounting semiconductor device Oct 20, 2019 Issued
Array ( [id] => 17232327 [patent_doc_number] => 20210358884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/287187 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287187 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287187
SEMICONDUCTOR DEVICE MANUFACTURING METHOD Oct 17, 2019 Abandoned
Array ( [id] => 17758137 [patent_doc_number] => 11398436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Module having sealing layer with recess [patent_app_type] => utility [patent_app_number] => 16/601777 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 12855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601777
Module having sealing layer with recess Oct 14, 2019 Issued
Array ( [id] => 17700369 [patent_doc_number] => 11374104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Methods of reducing capacitance in field-effect transistors [patent_app_type] => utility [patent_app_number] => 16/587474 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 9586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587474
Methods of reducing capacitance in field-effect transistors Sep 29, 2019 Issued
Array ( [id] => 17493431 [patent_doc_number] => 11282744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Enhanced intermetal dielectric adhesion [patent_app_type] => utility [patent_app_number] => 16/587071 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587071
Enhanced intermetal dielectric adhesion Sep 29, 2019 Issued
Array ( [id] => 16731484 [patent_doc_number] => 20210098632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => LOCALIZED PROTECTION LAYER FOR LASER ANNEALING PROCESS [patent_app_type] => utility [patent_app_number] => 16/586790 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586790
Localized protection layer for laser annealing process Sep 26, 2019 Issued
Array ( [id] => 16731212 [patent_doc_number] => 20210098360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => NTERCONNECT STRUCTURES AND METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 16/586279 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586279 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586279
Interconnect structures and methods of fabrication Sep 26, 2019 Issued
Array ( [id] => 16731239 [patent_doc_number] => 20210098387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METALLIZATION BARRIER STRUCTURES FOR BONDED INTEGRATED CIRCUIT INTERFACES [patent_app_type] => utility [patent_app_number] => 16/585666 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585666
Metallization barrier structures for bonded integrated circuit interfaces Sep 26, 2019 Issued
Array ( [id] => 16928324 [patent_doc_number] => 11049815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/584027 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 10811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584027 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584027
Semiconductor package Sep 25, 2019 Issued
Array ( [id] => 15717911 [patent_doc_number] => 20200105723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => MODULE [patent_app_type] => utility [patent_app_number] => 16/584902 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584902
MODULE Sep 25, 2019 Abandoned
Array ( [id] => 17477839 [patent_doc_number] => 20220085343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => METHOD FOR PREPARING QUANTUM DOTS LIGHT-EMITTING DIODE [patent_app_type] => utility [patent_app_number] => 17/419694 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17419694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/419694
Method for preparing quantum dots light-emitting diode Sep 16, 2019 Issued
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