Search

Marcus E Windrich

Examiner (ID: 3380, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3619, 3646
Total Applications
816
Issued Applications
604
Pending Applications
68
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18308448 [patent_doc_number] => 20230112348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => TUNNELING DEVICE HAVING INTERMEDIATE LAYER USING NATURAL OXIDE FILM AND METHOD OF MANUFACTURING TUNNELING DEVICE [patent_app_type] => utility [patent_app_number] => 17/909055 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17909055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/909055
TUNNELING DEVICE HAVING INTERMEDIATE LAYER USING NATURAL OXIDE FILM AND METHOD OF MANUFACTURING TUNNELING DEVICE Jun 6, 2021 Pending
Array ( [id] => 17389646 [patent_doc_number] => 20220037498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => Transistor Gate Structures and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/336599 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336599
Transistor Gate Structures and Methods of Forming the Same Jun 1, 2021 Pending
Array ( [id] => 17993703 [patent_doc_number] => 20220359740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => HEMT AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/335049 [patent_app_country] => US [patent_app_date] => 2021-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335049
HEMT AND METHOD OF FABRICATING THE SAME May 30, 2021 Pending
Array ( [id] => 18040304 [patent_doc_number] => 20220384521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => ALIGNMENT MARK FOR MRAM DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/330697 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330697
ALIGNMENT MARK FOR MRAM DEVICE AND METHOD May 25, 2021 Pending
Array ( [id] => 17708800 [patent_doc_number] => 20220208808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => IMAGE SENSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/329492 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329492
IMAGE SENSING DEVICE May 24, 2021 Pending
Array ( [id] => 17373863 [patent_doc_number] => 20220028915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => IMAGE SENSOR INCLUDING A BACK VIA STACK [patent_app_type] => utility [patent_app_number] => 17/327885 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/327885
Image sensor including a back via stack May 23, 2021 Issued
Array ( [id] => 18008928 [patent_doc_number] => 20220367695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => CIRCUITS AND GROUP III-NITRIDE TRANSISTORS WITH BURIED P-LAYERS AND CONTROLLED GATE VOLTAGES AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/321963 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321963
CIRCUITS AND GROUP III-NITRIDE TRANSISTORS WITH BURIED P-LAYERS AND CONTROLLED GATE VOLTAGES AND METHODS THEREOF May 16, 2021 Pending
Array ( [id] => 17055787 [patent_doc_number] => 20210265221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE USING DEHYDRATING CHEMICAL, AND METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/314521 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314521
METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE USING DEHYDRATING CHEMICAL, AND METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE May 6, 2021 Pending
Array ( [id] => 17993702 [patent_doc_number] => 20220359739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => HOLE DRAINING STRUCTURE FOR SUPPRESSION OF HOLE ACCUMULATION [patent_app_type] => utility [patent_app_number] => 17/308854 [patent_app_country] => US [patent_app_date] => 2021-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/308854
HOLE DRAINING STRUCTURE FOR SUPPRESSION OF HOLE ACCUMULATION May 4, 2021 Pending
Array ( [id] => 17986121 [patent_doc_number] => 20220352158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => STACKED DEVICE STRUCTURES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/242756 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242756 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242756
STACKED DEVICE STRUCTURES AND METHODS FOR FORMING THE SAME Apr 27, 2021 Pending
Array ( [id] => 17417163 [patent_doc_number] => 20220052067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/241343 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241343
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME Apr 26, 2021 Pending
Array ( [id] => 17189172 [patent_doc_number] => 20210336057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE [patent_app_type] => utility [patent_app_number] => 17/241318 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241318
STRAINED SEMICONDUCTOR MONOCRYSTALLINE NANOSTRUCTURE Apr 26, 2021 Pending
Array ( [id] => 17188713 [patent_doc_number] => 20210335598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/240101 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240101
PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS Apr 25, 2021 Pending
Array ( [id] => 17509035 [patent_doc_number] => 20220102138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Interconnect Structure for Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/232465 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232465
Interconnect Structure for Semiconductor Devices Apr 15, 2021 Pending
Array ( [id] => 17174086 [patent_doc_number] => 20210327757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/229137 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229137
Semiconductor chip and method for manufacturing the same Apr 12, 2021 Issued
Array ( [id] => 17901035 [patent_doc_number] => 20220310697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/228720 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/228720
Semiconductor memory device and fabrication method thereof Apr 12, 2021 Issued
Array ( [id] => 17174268 [patent_doc_number] => 20210327939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => PHOTOELECTRIC CONVERSION APPARATUS AND EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/224988 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224988
PHOTOELECTRIC CONVERSION APPARATUS AND EQUIPMENT Apr 6, 2021 Pending
Array ( [id] => 17485883 [patent_doc_number] => 20220093387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING AIR GAP [patent_app_type] => utility [patent_app_number] => 17/222195 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222195
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING AIR GAP Apr 4, 2021 Pending
Array ( [id] => 17145167 [patent_doc_number] => 20210313180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => PHOTOVOLTAIC CELL DEVICE AND MANUFACTURING METHOD OF TEMPLATE THEREOF [patent_app_type] => utility [patent_app_number] => 17/218378 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218378
PHOTOVOLTAIC CELL DEVICE AND MANUFACTURING METHOD OF TEMPLATE THEREOF Mar 30, 2021 Pending
Array ( [id] => 17917758 [patent_doc_number] => 20220320154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PHOTODIODE STRUCTURE FOR IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/217026 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217026
PHOTODIODE STRUCTURE FOR IMAGE SENSOR Mar 29, 2021 Pending
Menu