Search

Marcus E. Windrich

Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3646, 3619
Total Applications
906
Issued Applications
670
Pending Applications
85
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13283353 [patent_doc_number] => 10153268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Organic surface treatments for display glasses to reduce ESD [patent_app_type] => utility [patent_app_number] => 15/502535 [patent_app_country] => US [patent_app_date] => 2015-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6567 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15502535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/502535
Organic surface treatments for display glasses to reduce ESD Aug 6, 2015 Issued
Array ( [id] => 10732975 [patent_doc_number] => 20160079125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/812137 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 10689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812137 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812137
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME Jul 28, 2015 Abandoned
Array ( [id] => 10681516 [patent_doc_number] => 20160027661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD' [patent_app_type] => utility [patent_app_number] => 14/799623 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/799623
Heat treatment apparatus and heat treatment method Jul 14, 2015 Issued
Array ( [id] => 13909009 [patent_doc_number] => 20190043709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD FOR GALLIUM NITRIDE ON DIAMOND SEMICONDUCTOR WAFER PRODUCTION [patent_app_type] => utility [patent_app_number] => 14/800387 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800387 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800387
Method for gallium nitride on diamond semiconductor wafer production Jul 14, 2015 Issued
Array ( [id] => 11125502 [patent_doc_number] => 20160322476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'METHOD OF MANUFACTURING A FIN FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/792579 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3497 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792579 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792579
METHOD OF MANUFACTURING A FIN FIELD EFFECT TRANSISTOR Jul 5, 2015 Abandoned
Array ( [id] => 10732935 [patent_doc_number] => 20160079085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/751309 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751309
Semiconductor manufacturing method and semiconductor manufacturing apparatus Jun 25, 2015 Issued
Array ( [id] => 11110987 [patent_doc_number] => 20160307957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'WAFER LEVEL OPTOELECTRONIC DEVICE PACKAGES WITH CROSSTALK BARRIERS AND METHODS FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/748904 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11758 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748904 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/748904
Wafer level optoelectronic device packages with crosstalk barriers and methods for making the same Jun 23, 2015 Issued
Array ( [id] => 11000036 [patent_doc_number] => 20160196982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/742368 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 13058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742368 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742368
Method of fabricating semiconductor device Jun 16, 2015 Issued
Array ( [id] => 11564683 [patent_doc_number] => 09627278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Method of source/drain height control in dual epi finFET formation' [patent_app_type] => utility [patent_app_number] => 14/741418 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2469 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741418 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741418
Method of source/drain height control in dual epi finFET formation Jun 15, 2015 Issued
Array ( [id] => 11883644 [patent_doc_number] => 09754824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Tungsten films having low fluorine content' [patent_app_type] => utility [patent_app_number] => 14/723275 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723275
Tungsten films having low fluorine content May 26, 2015 Issued
Array ( [id] => 10752993 [patent_doc_number] => 20160099145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'COMPOSITION FOR FORMING SILICA LAYER, SILICA LAYER, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/720674 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5393 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720674 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/720674
Composition for forming silica layer, silica layer, and electronic device May 21, 2015 Issued
Array ( [id] => 10703235 [patent_doc_number] => 20160049382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE AND WIRE BONDING APPARATUS FOR PERFORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/718438 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718438 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718438
Method of manufacturing a semiconductor package and wire bonding apparatus for performing the same May 20, 2015 Issued
Array ( [id] => 11802310 [patent_doc_number] => 09543205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/712170 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 6779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712170
Method of fabricating semiconductor device May 13, 2015 Issued
Array ( [id] => 11453152 [patent_doc_number] => 09576803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor manufacturing process' [patent_app_type] => utility [patent_app_number] => 14/710619 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2987 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14710619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/710619
Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor manufacturing process May 12, 2015 Issued
Array ( [id] => 11292121 [patent_doc_number] => 20160342053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'ARRAY SUBSTRATE, REPAIRING SHEET, DISPLAY PANEL AND METHOD OF REPAIRING ARRAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/786187 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4067 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14786187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/786187
Array substrate, repairing sheet, display panel and method of repairing array substrate May 12, 2015 Issued
Array ( [id] => 10689619 [patent_doc_number] => 20160035765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'METHOD OF FABRICATING METAL WIRING AND THIN FILM TRANSISTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/706858 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5058 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706858
METHOD OF FABRICATING METAL WIRING AND THIN FILM TRANSISTOR SUBSTRATE May 6, 2015 Abandoned
Array ( [id] => 10809560 [patent_doc_number] => 20160155719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'CHIP BONDING APPARATUS AND CHIP BONDING METHOD' [patent_app_type] => utility [patent_app_number] => 14/706752 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706752
Chip bonding apparatus and chip bonding method May 6, 2015 Issued
Array ( [id] => 11489361 [patent_doc_number] => 09595434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Apparatus and methods for manufacturing semiconductor devices and treating substrates' [patent_app_type] => utility [patent_app_number] => 14/704912 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/704912
Apparatus and methods for manufacturing semiconductor devices and treating substrates May 4, 2015 Issued
Array ( [id] => 12954154 [patent_doc_number] => 09837532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Laterally diffused metal oxide semiconductor device and manufacturing method therefor [patent_app_type] => utility [patent_app_number] => 15/119868 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2360 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15119868 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/119868
Laterally diffused metal oxide semiconductor device and manufacturing method therefor May 3, 2015 Issued
Array ( [id] => 11740121 [patent_doc_number] => 09704714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Method for controlling surface charge on wafer surface in semiconductor fabrication' [patent_app_type] => utility [patent_app_number] => 14/688191 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6108 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688191 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688191
Method for controlling surface charge on wafer surface in semiconductor fabrication Apr 15, 2015 Issued
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