Search

Marcus E. Windrich

Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3646, 3619
Total Applications
906
Issued Applications
670
Pending Applications
85
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11293814 [patent_doc_number] => 20160343746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'DOPING METHOD AND DOPING APPARATUS OF ARRAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/426251 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426251 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426251
DOPING METHOD AND DOPING APPARATUS OF ARRAY SUBSTRATE Dec 29, 2014 Abandoned
Array ( [id] => 12477597 [patent_doc_number] => 09991120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Dilution doped integrated circuit resistors [patent_app_type] => utility [patent_app_number] => 14/576680 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3261 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576680
Dilution doped integrated circuit resistors Dec 18, 2014 Issued
Array ( [id] => 10984147 [patent_doc_number] => 20160181093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'III-N EPITAXY ON MULTILAYER BUFFER WITH PROTECTIVE TOP LAYER' [patent_app_type] => utility [patent_app_number] => 14/576500 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2222 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576500
III-N EPITAXY ON MULTILAYER BUFFER WITH PROTECTIVE TOP LAYER Dec 18, 2014 Abandoned
Array ( [id] => 10302596 [patent_doc_number] => 20150187597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS' [patent_app_type] => utility [patent_app_number] => 14/576617 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576617
METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS Dec 18, 2014 Abandoned
Array ( [id] => 11510175 [patent_doc_number] => 09601341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Method of etching' [patent_app_type] => utility [patent_app_number] => 14/577442 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2771 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577442 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577442
Method of etching Dec 18, 2014 Issued
Array ( [id] => 11466847 [patent_doc_number] => 09583488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow' [patent_app_type] => utility [patent_app_number] => 14/576659 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1878 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576659
Poly gate extension design methodology to improve CMOS performance in dual stress liner process flow Dec 18, 2014 Issued
Array ( [id] => 10440648 [patent_doc_number] => 20150325660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'CRYSTALLINE MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/578072 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578072
Crystalline multilayer structure and semiconductor device Dec 18, 2014 Issued
Array ( [id] => 11118240 [patent_doc_number] => 20160315215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'WEB BASED CHEMICAL BATH DEPOSITION APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/102569 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102569
Web based chemical bath deposition apparatus Dec 18, 2014 Issued
Array ( [id] => 11357236 [patent_doc_number] => 09533878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Low stress compact device packages' [patent_app_type] => utility [patent_app_number] => 14/567801 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/567801
Low stress compact device packages Dec 10, 2014 Issued
Array ( [id] => 10813482 [patent_doc_number] => 20160159642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'STRESS ISOLATED MEMS DEVICE WITH ASIC AS CAP' [patent_app_type] => utility [patent_app_number] => 14/564340 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564340
STRESS ISOLATED MEMS DEVICE WITH ASIC AS CAP Dec 8, 2014 Abandoned
Array ( [id] => 10277220 [patent_doc_number] => 20150162217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SYSTEM AND METHOD FOR MANUFACTURING A FABRICATED CARRIER' [patent_app_type] => utility [patent_app_number] => 14/561493 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 3824 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561493 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561493
System and method for manufacturing a fabricated carrier Dec 4, 2014 Issued
Array ( [id] => 11911139 [patent_doc_number] => 09779958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of, and apparatus for, forming hard mask' [patent_app_type] => utility [patent_app_number] => 14/560659 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7404 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560659
Method of, and apparatus for, forming hard mask Dec 3, 2014 Issued
Array ( [id] => 11432156 [patent_doc_number] => 09570482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Manufacturing method and manufacturing equipment of thin film transistor substrate' [patent_app_type] => utility [patent_app_number] => 14/407865 [patent_app_country] => US [patent_app_date] => 2014-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9772 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14407865 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/407865
Manufacturing method and manufacturing equipment of thin film transistor substrate Nov 27, 2014 Issued
Array ( [id] => 11346328 [patent_doc_number] => 09530744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/554550 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 6412 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554550
Semiconductor device and method of manufacturing the same Nov 25, 2014 Issued
Array ( [id] => 11101028 [patent_doc_number] => 20160297997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'METHOD AND DEVICE FOR POLYMERIZING A COMPOSITION COMPRISING HYDRIDOSILANES AND SUBSEQUENTLY USING THE POLYMERS TO PRODUCE SILICON-CONTAINING LAYERS' [patent_app_type] => utility [patent_app_number] => 15/100831 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15100831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/100831
Method and device for polymerizing a composition comprising hydridosilanes and subsequently using the polymers to produce silicon-containing layers Nov 25, 2014 Issued
Array ( [id] => 11050773 [patent_doc_number] => 20160247732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'ELECTRONIC DEVICES INCLUDING ORGANIC MATERIALS' [patent_app_type] => utility [patent_app_number] => 15/026145 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3949 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15026145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/026145
Electronic devices including organic materials Oct 6, 2014 Issued
Array ( [id] => 10747521 [patent_doc_number] => 20160093672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'LOGIC HIGH-K/METAL GATE 1T-1C RRAM MTP/OTP DEVICES' [patent_app_type] => utility [patent_app_number] => 14/499004 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499004 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499004
LOGIC HIGH-K/METAL GATE 1T-1C RRAM MTP/OTP DEVICES Sep 25, 2014 Abandoned
Array ( [id] => 10385504 [patent_doc_number] => 20150270511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Light Emitting Module and Lighting Apparatus' [patent_app_type] => utility [patent_app_number] => 14/491275 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/491275
Light Emitting Module and Lighting Apparatus Sep 18, 2014 Abandoned
Array ( [id] => 10681560 [patent_doc_number] => 20160027705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'METHODS AND STRUCTURES FOR DETECTING LOW STRENGTH IN AN INTERLAYER DIELECTRIC STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/341294 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14341294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/341294
Methods and structures for detecting low strength in an interlayer dielectric structure Jul 24, 2014 Issued
Array ( [id] => 11694340 [patent_doc_number] => 20170170057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD OF MANUFACTURING 3-D SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/306225 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4286 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15306225 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/306225
Method of manufacturing 3-D semiconductor device Jul 9, 2014 Issued
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