Search

Marcus E. Windrich

Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3646, 3619
Total Applications
906
Issued Applications
670
Pending Applications
85
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10487208 [patent_doc_number] => 20150372228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'Memory Device Having Oxygen Control Layers And Manufacturing Method Of Same' [patent_app_type] => utility [patent_app_number] => 14/309665 [patent_app_country] => US [patent_app_date] => 2014-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2905 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14309665 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/309665
Memory device having oxygen control layers and manufacturing method of same Jun 18, 2014 Issued
Array ( [id] => 11208019 [patent_doc_number] => 09437652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'CMOS compatible thermopile with low impedance contact' [patent_app_type] => utility [patent_app_number] => 14/292281 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292281
CMOS compatible thermopile with low impedance contact May 29, 2014 Issued
Array ( [id] => 11279830 [patent_doc_number] => 09496313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'CMOS-based thermopile with reduced thermal conductance' [patent_app_type] => utility [patent_app_number] => 14/292198 [patent_app_country] => US [patent_app_date] => 2014-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7199 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14292198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/292198
CMOS-based thermopile with reduced thermal conductance May 29, 2014 Issued
Array ( [id] => 11321623 [patent_doc_number] => 09520370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures' [patent_app_type] => utility [patent_app_number] => 14/282606 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14282606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/282606
Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures May 19, 2014 Issued
Array ( [id] => 10448015 [patent_doc_number] => 20150333028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'WAFER LEVEL PACAKGES HAVING NON-WETTABLE SOLDER COLLARS AND METHODS FOR THE FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/277343 [patent_app_country] => US [patent_app_date] => 2014-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14277343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/277343
Wafer level packages having non-wettable solder collars and methods for the fabrication thereof May 13, 2014 Issued
Array ( [id] => 10358561 [patent_doc_number] => 20150243566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'METHOD OF MEASURING CONTAMINATION AMOUNT OF VAPOR PHASE GROWTH APPARATUS, AND METHOD OF MANUFACTURING EPITAXIAL WAFER' [patent_app_type] => utility [patent_app_number] => 14/426968 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6008 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426968
Method of measuring contamination amount of vapor phase growth apparatus, and method of manufacturing epitaxial wafer Sep 25, 2013 Issued
Array ( [id] => 10395023 [patent_doc_number] => 20150280030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD FOR PRODUCING A PHOTOVOLTAIC CELL HAVING A HETEROJUNCTION, AND RESULTING PHOTOVOLTAIC CELL' [patent_app_type] => utility [patent_app_number] => 14/429654 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14429654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/429654
Method for producing a photovoltaic cell having a heterojunction, and resulting photovoltaic cell Sep 22, 2013 Issued
Array ( [id] => 10255761 [patent_doc_number] => 20150140758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'METHOD FOR FABRICATING FINFET ON GERMANIUM OR GROUP III-V SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/400511 [patent_app_country] => US [patent_app_date] => 2013-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3663 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14400511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/400511
METHOD FOR FABRICATING FINFET ON GERMANIUM OR GROUP III-V SEMICONDUCTOR SUBSTRATE Jul 7, 2013 Abandoned
Array ( [id] => 10241024 [patent_doc_number] => 20150126019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'METHOD FOR FABRICATING ACTIVE MATRIX SUBSTRATE AND METHOD FOR FABRICATING DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/401158 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5047 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14401158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/401158
Method for fabricating active matrix substrate and method for fabricating display device Jun 16, 2013 Issued
Array ( [id] => 10302505 [patent_doc_number] => 20150187505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD FOR MANUFACTURING SOLID ELECTROLYTIC CAPACITOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/403813 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5327 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14403813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/403813
Method for manufacturing solid electrolytic capacitor element May 22, 2013 Issued
Array ( [id] => 10247934 [patent_doc_number] => 20150132930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ANNEALING METHOD' [patent_app_type] => utility [patent_app_number] => 14/403566 [patent_app_country] => US [patent_app_date] => 2013-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5092 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14403566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/403566
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ANNEALING METHOD Apr 18, 2013 Abandoned
Array ( [id] => 10358759 [patent_doc_number] => 20150243764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/430337 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2557 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14430337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/430337
METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE Oct 22, 2012 Abandoned
Array ( [id] => 10285917 [patent_doc_number] => 20150170915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/395444 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14395444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/395444
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Sep 20, 2012 Abandoned
Array ( [id] => 11207843 [patent_doc_number] => 09437474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method for fabricating microelectronic devices with isolation trenches partially formed under active regions' [patent_app_type] => utility [patent_app_number] => 14/425891 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 5609 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14425891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/425891
Method for fabricating microelectronic devices with isolation trenches partially formed under active regions Sep 4, 2012 Issued
Array ( [id] => 10322046 [patent_doc_number] => 20150207050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/399710 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4116 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14399710 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/399710
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF May 7, 2012 Abandoned
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