Search

Marcus E. Windrich

Examiner (ID: 900, Phone: (571)272-6417 , Office: P/3646 )

Most Active Art Unit
3646
Art Unit(s)
3646, 3619
Total Applications
906
Issued Applications
670
Pending Applications
85
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19936819 [patent_doc_number] => 12310039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Semiconductor device including epitaxial electrode layer and dielectric epitaxial structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/692750 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692750
Semiconductor device including epitaxial electrode layer and dielectric epitaxial structure and method of manufacturing the same Mar 10, 2022 Issued
Array ( [id] => 17886559 [patent_doc_number] => 20220302037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => EMBEDDED PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/691403 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691403
Embedded packaging structure and manufacturing method thereof Mar 9, 2022 Issued
Array ( [id] => 18967420 [patent_doc_number] => 11901200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Light irradiation type heat treatment method and heat treatment apparatus [patent_app_type] => utility [patent_app_number] => 17/686415 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10595 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686415
Light irradiation type heat treatment method and heat treatment apparatus Mar 3, 2022 Issued
Array ( [id] => 18357814 [patent_doc_number] => 11646220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Raised via for terminal connections on different planes [patent_app_type] => utility [patent_app_number] => 17/650926 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 6213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650926
Raised via for terminal connections on different planes Feb 13, 2022 Issued
Array ( [id] => 20080923 [patent_doc_number] => 12355001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor package structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/669914 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 9481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669914 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669914
Semiconductor package structure and method for forming the same Feb 10, 2022 Issued
Array ( [id] => 18514629 [patent_doc_number] => 20230230889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => INTERCONNECTION ARRAY DEVICE WITH SUPPORT [patent_app_type] => utility [patent_app_number] => 17/579252 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579252
Interconnection array device with support Jan 18, 2022 Issued
Array ( [id] => 18298778 [patent_doc_number] => 20230108464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => PRINTED CIRCUIT BOARD AND ELECTRONIC COMPONENT PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/577687 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577687
Printed circuit board and electronic component package including the same Jan 17, 2022 Issued
Array ( [id] => 17752665 [patent_doc_number] => 20220230870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/574245 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574245
Method of manufacturing semiconductor device, substrate processing method, substrate processing apparatus, and recording medium Jan 11, 2022 Issued
Array ( [id] => 18348430 [patent_doc_number] => 20230136541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/568913 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568913
Electronic package and manufacturing method thereof Jan 4, 2022 Issued
Array ( [id] => 18488501 [patent_doc_number] => 20230215849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => PACKAGE SUBSTRATES WITH EMBEDDED DIE-SIDE, FACE-UP DEEP TRENCH CAPACITOR(S) (DTC(s)), AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 17/647141 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647141
PACKAGE SUBSTRATES WITH EMBEDDED DIE-SIDE, FACE-UP DEEP TRENCH CAPACITOR(S) (DTC(s)), AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS Jan 4, 2022 Abandoned
Array ( [id] => 17723598 [patent_doc_number] => 20220216320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => HEMT TRANSISTOR WITH IMPROVED GATE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/564831 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564831
HEMT transistor with improved gate arrangement Dec 28, 2021 Issued
Array ( [id] => 18473147 [patent_doc_number] => 20230207435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MULTILEVEL PACKAGE SUBSTRATE WITH STAIR SHAPED SUBSTRATE TRACES [patent_app_type] => utility [patent_app_number] => 17/563403 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563403
Multilevel package substrate with stair shaped substrate traces Dec 27, 2021 Issued
Array ( [id] => 19679467 [patent_doc_number] => 12191340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/558079 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 32451 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558079
Display device Dec 20, 2021 Issued
Array ( [id] => 18338974 [patent_doc_number] => 20230130923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/552911 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3591 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552911
SEMICONDUCTOR PACKAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE DEVICE Dec 15, 2021 Abandoned
Array ( [id] => 19945545 [patent_doc_number] => 12317697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Display panel and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/622823 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 1000 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/622823
Display panel and manufacturing method thereof Dec 13, 2021 Issued
Array ( [id] => 18440073 [patent_doc_number] => 20230187368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => HYBRID SEMICONDUCTOR PACKAGE FOR IMPROVED POWER INTEGRITY [patent_app_type] => utility [patent_app_number] => 17/548628 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548628
HYBRID SEMICONDUCTOR PACKAGE FOR IMPROVED POWER INTEGRITY Dec 12, 2021 Abandoned
Array ( [id] => 18439927 [patent_doc_number] => 20230187222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => ADAPTING ELECTRICAL, MECHANICAL, AND THERMAL PROPERTIES OF PACKAGE SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/549325 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549325
Adapting electrical, mechanical, and thermal properties of package substrates Dec 12, 2021 Issued
Array ( [id] => 17692173 [patent_doc_number] => 20220199466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT GROUP, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 17/547973 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547973
Semiconductor element, semiconductor element group, and method of manufacturing semiconductor element Dec 9, 2021 Issued
Array ( [id] => 17509382 [patent_doc_number] => 20220102485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/546248 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546248
Semiconductor device and manufacturing method of semiconductor device Dec 8, 2021 Issued
Array ( [id] => 17660813 [patent_doc_number] => 20220181278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => Antenna Chip Packaging Structure And Method For Preparing Same [patent_app_type] => utility [patent_app_number] => 17/546473 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546473
Antenna chip packaging structure and method for preparing same Dec 8, 2021 Issued
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