Search

Marcus Smith

Examiner (ID: 7124, Phone: (571)270-1096 , Office: P/2467 )

Most Active Art Unit
2467
Art Unit(s)
2616, 2468, 2419, 2467, 2619
Total Applications
664
Issued Applications
499
Pending Applications
20
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8227976 [patent_doc_number] => 20120142181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS' [patent_app_type] => utility [patent_app_number] => 13/369707 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369707 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369707
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Feb 8, 2012 Issued
Array ( [id] => 8217370 [patent_doc_number] => 20120133019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/368303 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2271 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/368303
Fuse of semiconductor device and method of forming the same Feb 6, 2012 Issued
Array ( [id] => 8210277 [patent_doc_number] => 20120129336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/360174 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5420 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20120129336.pdf [firstpage_image] =>[orig_patent_app_number] => 13360174 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/360174
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES Jan 26, 2012 Abandoned
Array ( [id] => 14301313 [patent_doc_number] => 10290791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Lighting device [patent_app_type] => utility [patent_app_number] => 13/985324 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5127 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985324 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/985324
Lighting device Jan 25, 2012 Issued
Array ( [id] => 11279773 [patent_doc_number] => 09496255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same' [patent_app_type] => utility [patent_app_number] => 13/356717 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3119 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13356717 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/356717
Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same Jan 23, 2012 Issued
Array ( [id] => 8893063 [patent_doc_number] => 20130166248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Monitor Test Key of Epi Profile' [patent_app_type] => utility [patent_app_number] => 13/336306 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3918 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13336306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/336306
Monitor test key of epi profile Dec 22, 2011 Issued
Array ( [id] => 10645501 [patent_doc_number] => 09362378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Piezoelectric devices and methods for their preparation and use' [patent_app_type] => utility [patent_app_number] => 13/583742 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4520 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13583742 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/583742
Piezoelectric devices and methods for their preparation and use Dec 19, 2011 Issued
Array ( [id] => 8094893 [patent_doc_number] => 20120083052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies' [patent_app_type] => utility [patent_app_number] => 13/323168 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20120083052.pdf [firstpage_image] =>[orig_patent_app_number] => 13323168 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/323168
Flexible packaging for chip-on-chip and package-on-package technologies Dec 11, 2011 Issued
Array ( [id] => 8789474 [patent_doc_number] => 20130106443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'SENSOR HAVING A TRANSISTOR AND IMPRINT SITES' [patent_app_type] => utility [patent_app_number] => 13/285828 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285828
SENSOR HAVING A TRANSISTOR AND IMPRINT SITES Oct 30, 2011 Abandoned
Array ( [id] => 9763060 [patent_doc_number] => 08847388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Bump with protection structure' [patent_app_type] => utility [patent_app_number] => 13/267200 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5335 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267200 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267200
Bump with protection structure Oct 5, 2011 Issued
Array ( [id] => 8753499 [patent_doc_number] => 20130087803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'MONOLITHICALLY INTEGRATED HEMT AND SCHOTTKY DIODE' [patent_app_type] => utility [patent_app_number] => 13/267552 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6922 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267552
MONOLITHICALLY INTEGRATED HEMT AND SCHOTTKY DIODE Oct 5, 2011 Abandoned
Array ( [id] => 8742613 [patent_doc_number] => 20130082330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Zener Diode Structure and Process' [patent_app_type] => utility [patent_app_number] => 13/250563 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250563 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/250563
Zener diode structure and process Sep 29, 2011 Issued
Array ( [id] => 7715639 [patent_doc_number] => 20120006262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'APPARATUS FOR FORMING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR FILM' [patent_app_type] => utility [patent_app_number] => 13/237001 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10195 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20120006262.pdf [firstpage_image] =>[orig_patent_app_number] => 13237001 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237001
Apparatus for forming thin film and method of manufacturing semiconductor film Sep 19, 2011 Issued
Array ( [id] => 9345515 [patent_doc_number] => 08664665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Schottky diode employing recesses for elements of junction barrier array' [patent_app_type] => utility [patent_app_number] => 13/229752 [patent_app_country] => US [patent_app_date] => 2011-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 8017 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229752 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229752
Schottky diode employing recesses for elements of junction barrier array Sep 10, 2011 Issued
Array ( [id] => 7706571 [patent_doc_number] => 20120001268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'ISOLATION WITH OFFSET DEEP WELL IMPLANTS' [patent_app_type] => utility [patent_app_number] => 13/228998 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228998
ISOLATION WITH OFFSET DEEP WELL IMPLANTS Sep 8, 2011 Abandoned
Array ( [id] => 7648778 [patent_doc_number] => 20110298047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE STRUCTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/212175 [patent_app_country] => US [patent_app_date] => 2011-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12908 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298047.pdf [firstpage_image] =>[orig_patent_app_number] => 13212175 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/212175
Three-dimensional semiconductor device structures and methods Aug 17, 2011 Issued
Array ( [id] => 9552902 [patent_doc_number] => 08759954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Integrated circuit package system with offset stacked die' [patent_app_type] => utility [patent_app_number] => 13/197215 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4056 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13197215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/197215
Integrated circuit package system with offset stacked die Aug 2, 2011 Issued
Array ( [id] => 7648849 [patent_doc_number] => 20110298118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/196425 [patent_app_country] => US [patent_app_date] => 2011-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3877 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298118.pdf [firstpage_image] =>[orig_patent_app_number] => 13196425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/196425
SEMICONDUCTOR DEVICE Aug 1, 2011 Abandoned
Array ( [id] => 10410140 [patent_doc_number] => 20150295149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'LED PACKAGE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/235045 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7550 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14235045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/235045
LED PACKAGE AND METHOD FOR MANUFACTURING SAME Jul 24, 2011 Abandoned
Array ( [id] => 7755865 [patent_doc_number] => 20120028434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING ACID DIFFUSION' [patent_app_type] => utility [patent_app_number] => 13/185897 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20120028434.pdf [firstpage_image] =>[orig_patent_app_number] => 13185897 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185897
Method of manufacturing semiconductor device using acid diffusion Jul 18, 2011 Issued
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