Search

Marcus Smith

Examiner (ID: 7124, Phone: (571)270-1096 , Office: P/2467 )

Most Active Art Unit
2467
Art Unit(s)
2616, 2468, 2419, 2467, 2619
Total Applications
664
Issued Applications
499
Pending Applications
20
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6417456 [patent_doc_number] => 20100276810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/435306 [patent_app_country] => US [patent_app_date] => 2009-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20100276810.pdf [firstpage_image] =>[orig_patent_app_number] => 12435306 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/435306
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF May 3, 2009 Abandoned
Array ( [id] => 6440686 [patent_doc_number] => 20100279436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Inspection Method For Integrated Circuit Manufacturing Processes' [patent_app_type] => utility [patent_app_number] => 12/433525 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20100279436.pdf [firstpage_image] =>[orig_patent_app_number] => 12433525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/433525
Inspection Method For Integrated Circuit Manufacturing Processes Apr 29, 2009 Abandoned
Array ( [id] => 5483309 [patent_doc_number] => 20090273074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'Bond wire loop for high speed noise isolation' [patent_app_type] => utility [patent_app_number] => 12/387133 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273074.pdf [firstpage_image] =>[orig_patent_app_number] => 12387133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/387133
Bond wire loop for high speed noise isolation Apr 26, 2009 Abandoned
Array ( [id] => 8808334 [patent_doc_number] => 08445987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Semiconductor device having a lower-layer line' [patent_app_type] => utility [patent_app_number] => 12/385839 [patent_app_country] => US [patent_app_date] => 2009-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12385839 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385839
Semiconductor device having a lower-layer line Apr 20, 2009 Issued
Array ( [id] => 9216692 [patent_doc_number] => 08629495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'High frequency field-effect transistor' [patent_app_type] => utility [patent_app_number] => 12/937701 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 11207 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12937701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/937701
High frequency field-effect transistor Apr 14, 2009 Issued
Array ( [id] => 8653427 [patent_doc_number] => 08373176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/937450 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 15608 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12937450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/937450
Semiconductor device and method of manufacturing the same Apr 8, 2009 Issued
Array ( [id] => 7741753 [patent_doc_number] => 08106396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Thin film transistor array substrate' [patent_app_type] => utility [patent_app_number] => 12/419306 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3828 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106396.pdf [firstpage_image] =>[orig_patent_app_number] => 12419306 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/419306
Thin film transistor array substrate Apr 6, 2009 Issued
Array ( [id] => 8749373 [patent_doc_number] => 08415204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Integrated circuit packaging system with heat spreader and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/412315 [patent_app_country] => US [patent_app_date] => 2009-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12412315 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/412315
Integrated circuit packaging system with heat spreader and method of manufacture thereof Mar 25, 2009 Issued
Array ( [id] => 5993124 [patent_doc_number] => 20110014777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD FOR PROCESSING A SUBSTRATE, METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP HAVING A RESIN ADHESIVE LAYER' [patent_app_type] => utility [patent_app_number] => 12/921252 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7443 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20110014777.pdf [firstpage_image] =>[orig_patent_app_number] => 12921252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/921252
Method for processing a substrate, method for manufacturing a semiconductor chip, and method for manufacturing a semiconductor chip having a resin adhesive layer Mar 23, 2009 Issued
Array ( [id] => 5953256 [patent_doc_number] => 20110033958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'METHOD FOR FORMING OXIDE FILM ON SILICON WAFER' [patent_app_type] => utility [patent_app_number] => 12/921492 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4262 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20110033958.pdf [firstpage_image] =>[orig_patent_app_number] => 12921492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/921492
Method for forming oxide film on silicon wafer Mar 23, 2009 Issued
Array ( [id] => 6149387 [patent_doc_number] => 20110020982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METHOD FOR BONDING OF CHIPS ON WAFERS' [patent_app_type] => utility [patent_app_number] => 12/736040 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20110020982.pdf [firstpage_image] =>[orig_patent_app_number] => 12736040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/736040
Method for bonding of chips on wafers Mar 12, 2009 Issued
Array ( [id] => 6519465 [patent_doc_number] => 20100230825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies' [patent_app_type] => utility [patent_app_number] => 12/402633 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230825.pdf [firstpage_image] =>[orig_patent_app_number] => 12402633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402633
Flexible packaging for chip-on-chip and package-on-package technologies Mar 11, 2009 Issued
Array ( [id] => 7518783 [patent_doc_number] => 07972884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Micromechanical device and method of manufacturing micromechanical device' [patent_app_type] => utility [patent_app_number] => 12/399348 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 4388 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/972/07972884.pdf [firstpage_image] =>[orig_patent_app_number] => 12399348 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399348
Micromechanical device and method of manufacturing micromechanical device Mar 5, 2009 Issued
Array ( [id] => 5435713 [patent_doc_number] => 20090170300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/395523 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6792 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170300.pdf [firstpage_image] =>[orig_patent_app_number] => 12395523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395523
SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF Feb 26, 2009 Abandoned
Array ( [id] => 5432748 [patent_doc_number] => 20090167334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Controlled Impedance Structures for High Density Interconnections' [patent_app_type] => utility [patent_app_number] => 12/348273 [patent_app_country] => US [patent_app_date] => 2009-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5677 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20090167334.pdf [firstpage_image] =>[orig_patent_app_number] => 12348273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348273
Controlled impedance structures for high density interconnections Jan 1, 2009 Issued
Array ( [id] => 5394958 [patent_doc_number] => 20090315021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 12/346603 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315021.pdf [firstpage_image] =>[orig_patent_app_number] => 12346603 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346603
DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS Dec 29, 2008 Abandoned
Array ( [id] => 5439343 [patent_doc_number] => 20090090982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Ultra-abrupt semiconductor junction profile' [patent_app_type] => utility [patent_app_number] => 12/316167 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20090090982.pdf [firstpage_image] =>[orig_patent_app_number] => 12316167 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/316167
Ultra-abrupt semiconductor junction profile Dec 9, 2008 Abandoned
Array ( [id] => 4460217 [patent_doc_number] => 07934314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Conductive film structure, fabrication method thereof, and conductive film type probe device for IC' [patent_app_type] => utility [patent_app_number] => 12/323422 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5057 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934314.pdf [firstpage_image] =>[orig_patent_app_number] => 12323422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323422
Conductive film structure, fabrication method thereof, and conductive film type probe device for IC Nov 24, 2008 Issued
Array ( [id] => 8955732 [patent_doc_number] => 08501504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 12/291738 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6970 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12291738 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/291738
Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer Nov 11, 2008 Issued
Array ( [id] => 5278650 [patent_doc_number] => 20090130782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'METHOD AND LINE FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/266725 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20090130782.pdf [firstpage_image] =>[orig_patent_app_number] => 12266725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/266725
METHOD AND LINE FOR MANUFACTURING SEMICONDUCTOR DEVICE Nov 6, 2008 Abandoned
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