Search

Marcus Smith

Examiner (ID: 7124, Phone: (571)270-1096 , Office: P/2467 )

Most Active Art Unit
2467
Art Unit(s)
2616, 2468, 2419, 2467, 2619
Total Applications
664
Issued Applications
499
Pending Applications
20
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6371436 [patent_doc_number] => 20100300522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'FABRICATION OF CONTACTS FOR SILICON SOLAR CELLS INCLUDING PRINTING BURN THROUGH LAYERS' [patent_app_type] => utility [patent_app_number] => 12/745400 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20100300522.pdf [firstpage_image] =>[orig_patent_app_number] => 12745400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/745400
Fabrication of contacts for silicon solar cells including printing burn through layers Nov 2, 2008 Issued
Array ( [id] => 52942 [patent_doc_number] => 07772066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'DRAM tunneling access transistor' [patent_app_type] => utility [patent_app_number] => 12/255186 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4029 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772066.pdf [firstpage_image] =>[orig_patent_app_number] => 12255186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/255186
DRAM tunneling access transistor Oct 20, 2008 Issued
Array ( [id] => 5549895 [patent_doc_number] => 20090283881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-DOWN ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/243246 [patent_app_country] => US [patent_app_date] => 2008-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3961 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283881.pdf [firstpage_image] =>[orig_patent_app_number] => 12243246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/243246
SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-DOWN ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME Sep 30, 2008 Abandoned
Array ( [id] => 5518506 [patent_doc_number] => 20090026487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'LIGHT-EMITTING DEVICES HAVING AN ACTIVE REGION WITH ELECTRICAL CONTACTS COUPLED TO OPPOSING SURFACES THEREOF AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/241665 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3250 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20090026487.pdf [firstpage_image] =>[orig_patent_app_number] => 12241665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241665
LIGHT-EMITTING DEVICES HAVING AN ACTIVE REGION WITH ELECTRICAL CONTACTS COUPLED TO OPPOSING SURFACES THEREOF AND METHODS OF FORMING THE SAME Sep 29, 2008 Abandoned
Array ( [id] => 6489591 [patent_doc_number] => 20100009487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'ONO Spacer Etch Process to Reduce Dark Current' [patent_app_type] => utility [patent_app_number] => 12/238696 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009487.pdf [firstpage_image] =>[orig_patent_app_number] => 12238696 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/238696
ONO spacer etch process to reduce dark current Sep 25, 2008 Issued
Array ( [id] => 8018113 [patent_doc_number] => 08138561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Structure and method to fabricate high performance MTJ devices for spin-transfer torque (STT)-RAM' [patent_app_type] => utility [patent_app_number] => 12/284066 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10350 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/138/08138561.pdf [firstpage_image] =>[orig_patent_app_number] => 12284066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/284066
Structure and method to fabricate high performance MTJ devices for spin-transfer torque (STT)-RAM Sep 17, 2008 Issued
Array ( [id] => 4850165 [patent_doc_number] => 20080315907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like' [patent_app_type] => utility [patent_app_number] => 12/200334 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6194 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315907.pdf [firstpage_image] =>[orig_patent_app_number] => 12200334 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/200334
Methods of operating an electronic circuit for measurement of transistor variability and the like Aug 27, 2008 Issued
Array ( [id] => 4469181 [patent_doc_number] => 07943404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Integrated millimeter wave antenna and transceiver on a substrate' [patent_app_type] => utility [patent_app_number] => 12/187436 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8314 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943404.pdf [firstpage_image] =>[orig_patent_app_number] => 12187436 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187436
Integrated millimeter wave antenna and transceiver on a substrate Aug 6, 2008 Issued
Array ( [id] => 4441930 [patent_doc_number] => 07927963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Integrated circuit structure, design structure, and method having improved isolation and harmonics' [patent_app_type] => utility [patent_app_number] => 12/187415 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7981 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/927/07927963.pdf [firstpage_image] =>[orig_patent_app_number] => 12187415 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187415
Integrated circuit structure, design structure, and method having improved isolation and harmonics Aug 6, 2008 Issued
Array ( [id] => 8457968 [patent_doc_number] => 08293634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Structures and methods for improving solder bump connections in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/187646 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 5349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12187646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187646
Structures and methods for improving solder bump connections in semiconductor devices Aug 6, 2008 Issued
Array ( [id] => 4469331 [patent_doc_number] => 07943447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Methods of fabricating crystalline silicon, thin film transistors, and solar cells' [patent_app_type] => utility [patent_app_number] => 12/184525 [patent_app_country] => US [patent_app_date] => 2008-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5793 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943447.pdf [firstpage_image] =>[orig_patent_app_number] => 12184525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184525
Methods of fabricating crystalline silicon, thin film transistors, and solar cells Jul 31, 2008 Issued
Array ( [id] => 5358559 [patent_doc_number] => 20090033353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'SYSTEMS AND METHODS FOR ELECTRICAL CHARACTERIZATION OF INTER-LAYER ALIGNMENT' [patent_app_type] => utility [patent_app_number] => 12/183418 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20090033353.pdf [firstpage_image] =>[orig_patent_app_number] => 12183418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183418
SYSTEMS AND METHODS FOR ELECTRICAL CHARACTERIZATION OF INTER-LAYER ALIGNMENT Jul 30, 2008 Abandoned
Array ( [id] => 4533195 [patent_doc_number] => 07888143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Apparatus and method for characterizing structures within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/182928 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888143.pdf [firstpage_image] =>[orig_patent_app_number] => 12182928 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182928
Apparatus and method for characterizing structures within an integrated circuit Jul 29, 2008 Issued
Array ( [id] => 8909358 [patent_doc_number] => 08481421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Functional anchors connecting graphene-like carbon to metal' [patent_app_type] => utility [patent_app_number] => 12/179345 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 46 [patent_no_of_words] => 14626 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12179345 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179345
Functional anchors connecting graphene-like carbon to metal Jul 23, 2008 Issued
Array ( [id] => 9153490 [patent_doc_number] => 08586396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Method for producing a silicon solar cell with a back-etched emitter as well as a corresponding solar cell' [patent_app_type] => utility [patent_app_number] => 12/670774 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6321 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12670774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/670774
Method for producing a silicon solar cell with a back-etched emitter as well as a corresponding solar cell Jul 22, 2008 Issued
Array ( [id] => 5413449 [patent_doc_number] => 20090039336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/176606 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 44700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20090039336.pdf [firstpage_image] =>[orig_patent_app_number] => 12176606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176606
SEMICONDUCTOR DEVICE Jul 20, 2008 Abandoned
Array ( [id] => 4792195 [patent_doc_number] => 20080293169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'LITHOGRAPHY EVALUATING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PROGRAM MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/167616 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20080293169.pdf [firstpage_image] =>[orig_patent_app_number] => 12167616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167616
LITHOGRAPHY EVALUATING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PROGRAM MEDIUM Jul 2, 2008 Abandoned
Array ( [id] => 4883914 [patent_doc_number] => 20080258246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES' [patent_app_type] => utility [patent_app_number] => 12/166623 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5755 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20080258246.pdf [firstpage_image] =>[orig_patent_app_number] => 12166623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166623
Passive electrically testable acceleration and voltage measurement devices Jul 1, 2008 Issued
Array ( [id] => 5296629 [patent_doc_number] => 20090011555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Method of manufacturing CMOS integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/216215 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3008 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20090011555.pdf [firstpage_image] =>[orig_patent_app_number] => 12216215 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216215
Method of manufacturing CMOS integrated circuit Jun 30, 2008 Abandoned
Array ( [id] => 5372063 [patent_doc_number] => 20090309623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Method for Assessment of Material Defects' [patent_app_type] => utility [patent_app_number] => 12/137151 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5645 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20090309623.pdf [firstpage_image] =>[orig_patent_app_number] => 12137151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137151
Method for Assessment of Material Defects Jun 10, 2008 Abandoned
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