Marcus Smith

Array ( [id] => 5490439 [patent_doc_number] => 20090291510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'METHOD FOR CREATING WAFER TEST PATTERN' [patent_app_type] => utility [patent_app_number] => 12/123546 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2696 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20090291510.pdf [firstpage_image] =>[orig_patent_app_number] => 12123546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8543251 [patent_doc_number] => 08318540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Method of manufacturing a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 12/122926 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 6884 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12122926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4778922 [patent_doc_number] => 20080286920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/122495 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2504 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20080286920.pdf [firstpage_image] =>[orig_patent_app_number] => 12122495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5310350 [patent_doc_number] => 20090017631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'SELF-ALIGNED PILLAR PATTERNING USING MULTIPLE SPACER MASKS' [patent_app_type] => utility [patent_app_number] => 12/119836 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20090017631.pdf [firstpage_image] =>[orig_patent_app_number] => 12119836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5555502 [patent_doc_number] => 20090267079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'EXTERNALLY CONFIGURABLE INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/110816 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9057 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267079.pdf [firstpage_image] =>[orig_patent_app_number] => 12110816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7730817 [patent_doc_number] => 08101996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Three-dimensional semiconductor device structures and methods' [patent_app_type] => utility [patent_app_number] => 12/103701 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 55 [patent_no_of_words] => 10668 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101996.pdf [firstpage_image] =>[orig_patent_app_number] => 12103701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4663677 [patent_doc_number] => 20080254584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'METHOD OF MANUFACTURING FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/102326 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254584.pdf [firstpage_image] =>[orig_patent_app_number] => 12102326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5455553 [patent_doc_number] => 20090255705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'Method of Creating Alignment/Centering Guides for Small Diameter, High Density Through-Wafer Via Die Stacking' [patent_app_type] => utility [patent_app_number] => 12/101776 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4854 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20090255705.pdf [firstpage_image] =>[orig_patent_app_number] => 12101776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4887007 [patent_doc_number] => 20080261339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'PACKAGING METHOD TO MANUFACTURE PACKAGE FOR A HIGH-POWER LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 12/062406 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2549 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20080261339.pdf [firstpage_image] =>[orig_patent_app_number] => 12062406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5469768 [patent_doc_number] => 20090242934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'Photodiode And Method Of Fabrication' [patent_app_type] => utility [patent_app_number] => 12/060342 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8376 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20090242934.pdf [firstpage_image] =>[orig_patent_app_number] => 12060342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715256 [patent_doc_number] => 20080237778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/053931 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237778.pdf [firstpage_image] =>[orig_patent_app_number] => 12053931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4805912 [patent_doc_number] => 20080169490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/053926 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 10481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20080169490.pdf [firstpage_image] =>[orig_patent_app_number] => 12053926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4752614 [patent_doc_number] => 20080160689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Three-Dimensional Control-Gate Architecture For Single Poly EPROM Memory Devices Fabricated In Planar CMOS Technology' [patent_app_type] => utility [patent_app_number] => 12/046913 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5129 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160689.pdf [firstpage_image] =>[orig_patent_app_number] => 12046913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 91984 [patent_doc_number] => 07732302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Integrated sensor and circuitry and process therefor' [patent_app_type] => utility [patent_app_number] => 12/033395 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 6293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732302.pdf [firstpage_image] =>[orig_patent_app_number] => 12033395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4904068 [patent_doc_number] => 20080113481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'CAPACITANCE DIELECTRIC LAYER, CAPACITOR AND FORMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/014735 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4431 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20080113481.pdf [firstpage_image] =>[orig_patent_app_number] => 12014735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4810655 [patent_doc_number] => 20080191286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Methods for manufacturing a CMOS device with dual dielectric layers' [patent_app_type] => utility [patent_app_number] => 11/972601 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8174 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191286.pdf [firstpage_image] =>[orig_patent_app_number] => 11972601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7775416 [patent_doc_number] => 08120061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Light receiving device' [patent_app_type] => utility [patent_app_number] => 12/522296 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8069 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120061.pdf [firstpage_image] =>[orig_patent_app_number] => 12522296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5435682 [patent_doc_number] => 20090170269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'HIGH VOLTAGE MOSFET DEVICES CONTAINING TIP COMPENSATION IMPLANT' [patent_app_type] => utility [patent_app_number] => 11/968135 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2874 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170269.pdf [firstpage_image] =>[orig_patent_app_number] => 11968135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5268553 [patent_doc_number] => 20090072328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/966582 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20090072328.pdf [firstpage_image] =>[orig_patent_app_number] => 11966582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5435681 [patent_doc_number] => 20090170268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS' [patent_app_type] => utility [patent_app_number] => 11/965415 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20090170268.pdf [firstpage_image] =>[orig_patent_app_number] => 11965415 [rel_patent_id] =>[rel_patent_doc_number] =>)