
Marcus Smith
Examiner (ID: 7124, Phone: (571)270-1096 , Office: P/2467 )
| Most Active Art Unit | 2467 |
| Art Unit(s) | 2616, 2468, 2419, 2467, 2619 |
| Total Applications | 664 |
| Issued Applications | 499 |
| Pending Applications | 20 |
| Abandoned Applications | 148 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4715930
[patent_doc_number] => 20080238452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'Vertical micro probes'
[patent_app_type] => utility
[patent_app_number] => 11/731072
[patent_app_country] => US
[patent_app_date] => 2007-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4194
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20080238452.pdf
[firstpage_image] =>[orig_patent_app_number] => 11731072
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/731072 | Vertical micro probes | Mar 29, 2007 | Abandoned |
Array
(
[id] => 4715139
[patent_doc_number] => 20080237661
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'ULTRA-ABRUPT SEMICONDUCTOR JUNCTION PROFILE'
[patent_app_type] => utility
[patent_app_number] => 11/694936
[patent_app_country] => US
[patent_app_date] => 2007-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3561
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20080237661.pdf
[firstpage_image] =>[orig_patent_app_number] => 11694936
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694936 | Ultra-abrupt semiconductor junction profile | Mar 29, 2007 | Issued |
Array
(
[id] => 4737607
[patent_doc_number] => 20080231259
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'INTERLOCKING ELECTRICAL TEST PROBES'
[patent_app_type] => utility
[patent_app_number] => 11/726750
[patent_app_country] => US
[patent_app_date] => 2007-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1236
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20080231259.pdf
[firstpage_image] =>[orig_patent_app_number] => 11726750
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/726750 | Interlocking electrical test probes | Mar 22, 2007 | Issued |
Array
(
[id] => 178472
[patent_doc_number] => 07656182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Testing method using a scalable parametric measurement macro'
[patent_app_type] => utility
[patent_app_number] => 11/689150
[patent_app_country] => US
[patent_app_date] => 2007-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7096
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/656/07656182.pdf
[firstpage_image] =>[orig_patent_app_number] => 11689150
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/689150 | Testing method using a scalable parametric measurement macro | Mar 20, 2007 | Issued |
Array
(
[id] => 4975209
[patent_doc_number] => 20070216439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'MOS transistor characteristic detection apparatus and CMOS circuit characteristic automatic adjustment apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/723234
[patent_app_country] => US
[patent_app_date] => 2007-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6558
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20070216439.pdf
[firstpage_image] =>[orig_patent_app_number] => 11723234
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/723234 | MOS transistor characteristic detection apparatus and CMOS circuit characteristic automatic adjustment apparatus | Mar 18, 2007 | Issued |
Array
(
[id] => 5163505
[patent_doc_number] => 20070285089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'CURRENT DETECTION PRINTED BOARD, VOLTAGE DETECTION PRINTED BOARD, CURRENT/VOLTAGE DETECTION PRINTED BOARD, CURRENT/VOLTAGE DETECTOR, CURRENT DETECTOR AND VOLTAGE DETECTOR'
[patent_app_type] => utility
[patent_app_number] => 11/687973
[patent_app_country] => US
[patent_app_date] => 2007-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 18906
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20070285089.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687973
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687973 | CURRENT DETECTION PRINTED BOARD, VOLTAGE DETECTION PRINTED BOARD, CURRENT/VOLTAGE DETECTION PRINTED BOARD, CURRENT/VOLTAGE DETECTOR, CURRENT DETECTOR AND VOLTAGE DETECTOR | Mar 18, 2007 | Abandoned |
Array
(
[id] => 4975199
[patent_doc_number] => 20070216429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'PROBE CARD, METHOD OF DESIGNING THE PROBE CARD, AND METHOD OF TESTING SEMICONDUCTOR CHIPS USING THE PROBE CARD'
[patent_app_type] => utility
[patent_app_number] => 11/685645
[patent_app_country] => US
[patent_app_date] => 2007-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3812
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20070216429.pdf
[firstpage_image] =>[orig_patent_app_number] => 11685645
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/685645 | PROBE CARD, METHOD OF DESIGNING THE PROBE CARD, AND METHOD OF TESTING SEMICONDUCTOR CHIPS USING THE PROBE CARD | Mar 12, 2007 | Abandoned |
Array
(
[id] => 9662203
[patent_doc_number] => 08809179
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Method for reducing topography of non-volatile memory and resulting memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/716164
[patent_app_country] => US
[patent_app_date] => 2007-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 4444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11716164
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/716164 | Method for reducing topography of non-volatile memory and resulting memory cells | Mar 8, 2007 | Issued |
Array
(
[id] => 4696002
[patent_doc_number] => 20080218186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'Image sensing integrated circuit test apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 11/715535
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4600
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0218/20080218186.pdf
[firstpage_image] =>[orig_patent_app_number] => 11715535
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/715535 | Image sensing integrated circuit test apparatus and method | Mar 6, 2007 | Abandoned |
Array
(
[id] => 63844
[patent_doc_number] => 07764072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-27
[patent_title] => 'Differential signal probing system'
[patent_app_type] => utility
[patent_app_number] => 11/710225
[patent_app_country] => US
[patent_app_date] => 2007-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 6553
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/764/07764072.pdf
[firstpage_image] =>[orig_patent_app_number] => 11710225
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/710225 | Differential signal probing system | Feb 21, 2007 | Issued |
Array
(
[id] => 1077471
[patent_doc_number] => 07615988
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-10
[patent_title] => 'Wide range current sensing method and system'
[patent_app_type] => utility
[patent_app_number] => 11/705373
[patent_app_country] => US
[patent_app_date] => 2007-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3790
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/615/07615988.pdf
[firstpage_image] =>[orig_patent_app_number] => 11705373
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/705373 | Wide range current sensing method and system | Feb 11, 2007 | Issued |
Array
(
[id] => 5003009
[patent_doc_number] => 20070200576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-30
[patent_title] => 'Multi-layered probes'
[patent_app_type] => utility
[patent_app_number] => 11/703875
[patent_app_country] => US
[patent_app_date] => 2007-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4396
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20070200576.pdf
[firstpage_image] =>[orig_patent_app_number] => 11703875
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/703875 | Multi-layered probes | Feb 6, 2007 | Abandoned |
Array
(
[id] => 311591
[patent_doc_number] => 07528623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Distributing data among test boards to determine test parameters'
[patent_app_type] => utility
[patent_app_number] => 11/670750
[patent_app_country] => US
[patent_app_date] => 2007-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5735
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/528/07528623.pdf
[firstpage_image] =>[orig_patent_app_number] => 11670750
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/670750 | Distributing data among test boards to determine test parameters | Feb 1, 2007 | Issued |
Array
(
[id] => 4843726
[patent_doc_number] => 20080180134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Electronic Circuit for Measurement of Transistor Variability and the Like'
[patent_app_type] => utility
[patent_app_number] => 11/669250
[patent_app_country] => US
[patent_app_date] => 2007-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6106
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20080180134.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669250
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669250 | Electronic circuit for measurement of transistor variability and the like | Jan 30, 2007 | Issued |
Array
(
[id] => 4845964
[patent_doc_number] => 20080182372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS'
[patent_app_type] => utility
[patent_app_number] => 11/669645
[patent_app_country] => US
[patent_app_date] => 2007-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1822
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20080182372.pdf
[firstpage_image] =>[orig_patent_app_number] => 11669645
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/669645 | METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS | Jan 30, 2007 | Abandoned |
Array
(
[id] => 178440
[patent_doc_number] => 07656150
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Test handler and loading method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/627276
[patent_app_country] => US
[patent_app_date] => 2007-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5047
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/656/07656150.pdf
[firstpage_image] =>[orig_patent_app_number] => 11627276
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/627276 | Test handler and loading method thereof | Jan 24, 2007 | Issued |
Array
(
[id] => 4763119
[patent_doc_number] => 20080174329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'METHOD AND DEVICE FOR DETERMINING AN OPERATIONAL LIFETIME OF AN INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/624258
[patent_app_country] => US
[patent_app_date] => 2007-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6184
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20080174329.pdf
[firstpage_image] =>[orig_patent_app_number] => 11624258
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/624258 | Method and device for determining an operational lifetime of an integrated circuit device | Jan 17, 2007 | Issued |
Array
(
[id] => 23603
[patent_doc_number] => 07795102
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-09-14
[patent_title] => 'ESD high frequency diodes'
[patent_app_type] => utility
[patent_app_number] => 11/654735
[patent_app_country] => US
[patent_app_date] => 2007-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1784
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/795/07795102.pdf
[firstpage_image] =>[orig_patent_app_number] => 11654735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/654735 | ESD high frequency diodes | Jan 16, 2007 | Issued |
Array
(
[id] => 9676839
[patent_doc_number] => 08815748
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Method of forming semiconductor device with multiple level patterning'
[patent_app_type] => utility
[patent_app_number] => 11/623036
[patent_app_country] => US
[patent_app_date] => 2007-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3913
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11623036
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/623036 | Method of forming semiconductor device with multiple level patterning | Jan 11, 2007 | Issued |
Array
(
[id] => 4805546
[patent_doc_number] => 20080169124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-17
[patent_title] => 'Padless via and method for making same'
[patent_app_type] => utility
[patent_app_number] => 11/652735
[patent_app_country] => US
[patent_app_date] => 2007-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3813
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0169/20080169124.pdf
[firstpage_image] =>[orig_patent_app_number] => 11652735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/652735 | Padless via and method for making same | Jan 11, 2007 | Abandoned |