Search

Mardochee Chery

Examiner (ID: 2604, Phone: (571)272-4246 , Office: P/2133 )

Most Active Art Unit
2133
Art Unit(s)
2186, 2188, 2133
Total Applications
1144
Issued Applications
964
Pending Applications
68
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20087344 [patent_doc_number] => 20250217280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => METHOD OF OPERATING STORAGE CONTROLLER, STORAGE DEVICE, AND METHOD OF OPERATING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/944859 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/944859
Method of operating storage controller, storage device, and method of operating storage device to perform copy-block operation based on number of corrected bits Nov 11, 2024 Issued
Array ( [id] => 20914218 [patent_doc_number] => 12711063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Memory device optimization for parallel data requests [patent_app_type] => utility [patent_app_number] => 18/941785 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941785
MEMORY DEVICE OPTIMIZATION FOR PARALLEL DATA REQUESTS Nov 7, 2024 Pending
Array ( [id] => 20695699 [patent_doc_number] => 20260127111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => Data Storage Device and Method for Selectively Performing a Program-Verify Operation [patent_app_type] => utility [patent_app_number] => 18/939779 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939779
Data storage device and method for selectively performing a program-verify operation Nov 6, 2024 Issued
Array ( [id] => 20717130 [patent_doc_number] => 12632381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Method of decommissioning a solid-state drive [patent_app_type] => utility [patent_app_number] => 18/939815 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939815
Method of decommissioning a solid-state drive Nov 6, 2024 Issued
Array ( [id] => 20026941 [patent_doc_number] => 20250165163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => OPERATING METHOD OF A NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/939210 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939210
Transaction validation and memory configuration modification Nov 5, 2024 Issued
Array ( [id] => 20703094 [patent_doc_number] => 12625806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Apparatus and methods for statically mapping random write command data [patent_app_type] => utility [patent_app_number] => 18/925125 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 14245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925125
Apparatus and methods for statically mapping random write command data Oct 23, 2024 Issued
Array ( [id] => 20395448 [patent_doc_number] => 20250370923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY SYSTEMS AND METHODS OF OPERATING THEREOF, AND COMPUTER READABLE STORAGE MEDIUMS [patent_app_type] => utility [patent_app_number] => 18/916192 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18916192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/916192
MEMORY SYSTEMS AND METHODS OF OPERATING THEREOF, AND COMPUTER READABLE STORAGE MEDIUMS Oct 14, 2024 Pending
Array ( [id] => 20395447 [patent_doc_number] => 20250370922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF, STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/912348 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18912348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/912348
Memory system and operating method thereof, storage medium Oct 9, 2024 Issued
Array ( [id] => 20914215 [patent_doc_number] => 12711060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Memory devices, operating methods and memory systems for managing bad memory blocks [patent_app_type] => utility [patent_app_number] => 18/912283 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18912283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/912283
MEMORY DEVICES, OPERATING METHODS AND MEMORY SYSTEMS Oct 9, 2024 Pending
Array ( [id] => 19864702 [patent_doc_number] => 20250103488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY DEVICE, CXL MEMORY DEVICE, SYSTEM IN PACKAGE, AND SYSTEM ON CHIP INCLUDING HIGH BANDWIDTH MEMORY [patent_app_type] => utility [patent_app_number] => 18/898068 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898068
Memory device, CXL memory device, system in package, and system on chip including high bandwidth memory Sep 25, 2024 Issued
Array ( [id] => 19864701 [patent_doc_number] => 20250103487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => NOR MEMORY AND READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/894101 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/894101
NOR MEMORY AND READING METHOD THEREOF Sep 23, 2024 Pending
Array ( [id] => 20570659 [patent_doc_number] => 20260064584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => LOOKUP TABLE FOR CONTIGUOUS PAGE DETECTION IN LIVE MIGRATION [patent_app_type] => utility [patent_app_number] => 18/888773 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888773 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888773
Lookup table for contiguous page detection in live migration Sep 17, 2024 Issued
Array ( [id] => 20154421 [patent_doc_number] => 20250254259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SECURE MEDIA TRANSFER APPLIANCE [patent_app_type] => utility [patent_app_number] => 18/885335 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/885335
SECURE MEDIA TRANSFER APPLIANCE Sep 12, 2024 Pending
Array ( [id] => 20758013 [patent_doc_number] => 12650782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Memory block utilization in memory systems [patent_app_type] => utility [patent_app_number] => 18/830260 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830260
Memory block utilization in memory systems Sep 9, 2024 Issued
Array ( [id] => 19660445 [patent_doc_number] => 20240427510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/829295 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829295
Memory system having a controller determining program fail count Sep 9, 2024 Issued
Array ( [id] => 20323264 [patent_doc_number] => 20250335352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MEMORY SYSTEMS AND OPERATION METHODS, ELECTRONIC APPARATUSES [patent_app_type] => utility [patent_app_number] => 18/825930 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/825930
Memory systems and operation methods, electronic apparatuses Sep 4, 2024 Issued
Array ( [id] => 20666533 [patent_doc_number] => 12608308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => In-memory partial checksum calculation with flexible media coverage [patent_app_type] => utility [patent_app_number] => 18/824845 [patent_app_country] => US [patent_app_date] => 2024-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/824845
In-memory partial checksum calculation with flexible media coverage Sep 3, 2024 Issued
Array ( [id] => 20507028 [patent_doc_number] => 12541304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Memory device, operation method thereof, memory system, and memory controller [patent_app_type] => utility [patent_app_number] => 18/821643 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 21550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821643
Memory device, operation method thereof, memory system, and memory controller Aug 29, 2024 Issued
Array ( [id] => 19756405 [patent_doc_number] => 20250044970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => HOST-ENABLED BLOCK SWAP TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/797447 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797447
Host-enabled block swap techniques Aug 6, 2024 Issued
Array ( [id] => 19747740 [patent_doc_number] => 20250036305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => EFFICIENT ERROR SIGNALING BY MEMORY [patent_app_type] => utility [patent_app_number] => 18/794882 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/794882
Efficient error signaling by memory Aug 4, 2024 Issued
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